From fb2562d3298e10595a38c5cffd1c2f748bfe7ea3 Mon Sep 17 00:00:00 2001
From: Uri Shaked <uri@urishaked.com>
Date: Thu, 20 Jul 2023 21:59:10 +0300
Subject: [PATCH] fix: broken verification

---
 caravel.py   | 37 -------------------------------------
 configure.py | 16 ++++++++--------
 2 files changed, 8 insertions(+), 45 deletions(-)

diff --git a/caravel.py b/caravel.py
index 8f45528..9d7e0ce 100644
--- a/caravel.py
+++ b/caravel.py
@@ -18,43 +18,6 @@ class CaravelConfig():
             for project in self.projects:
                 fh.write(f'`include "gl/{project.get_gl_verilog_filename()}"\n')
 
-        # build complete list of filenames for sim
-        with open('verilog/includes/includes.rtl.caravel_user_project', 'w') as fh:
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_top.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_ctrl.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_mux.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/tt_user_module.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_buf.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_dfrbp.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_diode.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_inv.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_mux4.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_tbuf_pol.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_tbuf.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/proto/prim_generic/tt_prim_zbuf.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/cells.v\n')
-            # for project in self.projects:
-            #     fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{project.get_top_verilog_filename()}\n')
-        with open('verilog/includes/includes.rtl.caravel_user_project.openlane2', 'w') as fh:
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/ol2/tt_top/user_project_wrapper.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_top.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_ctrl.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_mux.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/tt_user_module.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_buf.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_dfrbp.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_diode.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_inv.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_mux4.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tbuf_pol.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tbuf.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_tie.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/tt-multiplexer/rtl/prim_generic/tt_prim_zbuf.v\n')
-            fh.write('-v $(USER_PROJECT_VERILOG)/rtl/cells.v\n')
-            # for project in self.projects:
-            #     fh.write(f'-v $(USER_PROJECT_VERILOG)/rtl/{project.get_top_verilog_filename()}\n')
-
         # build GL includes
         with open('verilog/includes/includes.gl.caravel_user_project', 'w') as fh:
             fh.write('-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v\n')
diff --git a/configure.py b/configure.py
index 27d2a63..71d748f 100755
--- a/configure.py
+++ b/configure.py
@@ -19,18 +19,16 @@ class Projects():
     def __init__(self, config, args):
         self.args = args
         self.config = config
-
-        if args.test:
-            self.project_dir = config['test_project_dir']
-        else:
-            self.project_dir = config['project_dir']
+        self.project_dir = config['project_dir']
 
         if not os.path.exists(self.project_dir):
             os.makedirs(self.project_dir)
 
         self.projects = []
         project_list = [entry for entry in os.listdir(self.project_dir) if os.path.join(self.project_dir, entry)]
-        if args.sta_projects:
+        if args.test:
+            project_list = ['tt_um_factory_test']
+        elif args.sta_projects:
             project_list = ['tt_um_loopback']
 
         for index, project_id in enumerate(project_list):
@@ -193,8 +191,10 @@ if __name__ == '__main__':
 
     projects = Projects(config, args)
 
-    if args.sta_projects:
-        modules_yaml_name = "modules_sta.yaml"
+    if args.test:
+        modules_yaml_name = "modules.test.yaml"
+    elif args.sta_projects:
+        modules_yaml_name = "modules.sta.yaml"
     else:
         modules_yaml_name = "modules.yaml"