From fcf7e8a37f4224658b6c773f5281b58a25e88d0f Mon Sep 17 00:00:00 2001
From: Uri Shaked <uri@urishaked.com>
Date: Wed, 17 Sep 2025 11:56:14 +0300
Subject: [PATCH] fix(tt_tool): always specify the power pin names

Up to this point, we relied on the PDK's default power pin names. However, the defaults names for GF180, VDD and VSS, are not compatible with Tiny Tapeout, which expects VPWR (or VDPWR) and VGND. So instead, we set the VDD_PIN and GND_PIN config options explicitly.
---
 project.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/project.py b/project.py
index 683ff61..6859686 100644
--- a/project.py
+++ b/project.py
@@ -488,6 +488,8 @@ class Project:
             "VERILOG_FILES": [f"dir::{src}" for src in self.sources],
             "DIE_AREA": die_area,
             "FP_DEF_TEMPLATE": def_template,
+            "VDD_PIN": "VPWR",
+            "GND_PIN": "VGND",
             "RT_MAX_LAYER": self.tech.project_top_metal_layer,
         }
         write_config(config, os.path.join(self.src_dir, "user_config"), ("json",))