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fix mux address for print project metrics

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Matt Venn
2023-09-12 12:03:57 +02:00
parent 9818f61c41
commit fe20470ddd
3 changed files with 4 additions and 4 deletions
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docs/hugo_index_template.md
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@@ -23,10 +23,9 @@ description: 143 designs, closed 8th September 2023
* 143 projects
* build time for all projects 8.6 hours
* total cells 82126
* max cells 6813 for [project 089](./089)
* max utilisation 87.18% for [project 053](./053)
* max cells 6813 for [project 033](./033)
* max utilisation 87.18% for [project 016](./016)
* total wire length 2607 mm
* 94 used Wokwi, 135 Verilog, 1 myhdl, 7 Amaranth, spade 1, xls 2, migen 1, systemverilog 3, mixed radix circuit synthesis (mrcs) 1, chisel 1.
* 92 used Verilog, 46 Wokwi, 1 SystemVerilog, 1 SpinalHDL, 1 mrcs, 1 spade, 1 RustHDL
* top 10 tags:
- test : 18