From fe543406d6d5ce095362ca3dd2d4776fa0cbb13b Mon Sep 17 00:00:00 2001
From: Uri Shaked <uri@urishaked.com>
Date: Wed, 16 Apr 2025 17:12:34 +0300
Subject: [PATCH] fix(precheck): disable power pin check for IHP

IHP provided verilog models do not have power ports, so we don't use powered netlists, and thus no need to check for power pins in the GL verilog.
---
 precheck/precheck.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/precheck/precheck.py b/precheck/precheck.py
index 1a9fc27..77bf11a 100644
--- a/precheck/precheck.py
+++ b/precheck/precheck.py
@@ -370,6 +370,7 @@ def main():
         {
             "name": "Power pin check",
             "check": lambda: power_pin_check(verilog_file, lef_file, uses_3v3),
+            "tech": "sky130",
         },
         {"name": "Layer check", "check": lambda: layer_check(gds_file, tech)},
         {"name": "Cell name check", "check": lambda: cell_name_check(gds_file)},