47 Commits
Author SHA1 Message Date
Uri Shaked 617676148e feat(ihp-sg13cmos5l): analog project support 2026-10-29 21:32:06 +01:00
Uri Shaked 2278ea867e feat: add ihp-sg13cmos5l PDK alongside ihp-sg13g2
Based on work done in the ihp-sg13cmos5l branch
2026-10-27 11:17:19 +01:00
htfab d869909e41 fix(precheck): rewrite the boundary check
The previous version of the boundary check was a quick heuristic where
we compared the bounding box of the design to that of the prBoundary layer.
Over time we came across some designs where this is insufficient.

The new check compares the bounding box to the correct project size
based on the .def template and verifies that there is a rectangle of
this exact size in the prBoundary layer at the top level.

The patch also abstracts parsing the .def template into a separate
function since we now use it in two different checks.
2026-07-28 21:21:12 +02:00
Uri Shaked d1bbd34d95 feat(precheck/gf180mcuD): update to latest PDK 2026-06-14 20:23:49 +03:00
Uri Shaked 50998ec8f8 feat(precheck/gf180mcuD): run KLayout DRC via PDK run_drc.py
- Density related rules skipped (irrelevant for user projects)
- Add docopt dependecy (required by the PDK's run_drc.py)
2026-06-14 16:50:19 +03:00
Uri Shaked 1de6149a61 fix(precheck): disable gf180mcuD magic DRC
Sylvain: The techfile for GF180 is still a bit dodgy in some areas,
especially when reading from GDS and it's rejecting perfectly valid designs.
Wafer.space relies only on KLayout DRC for acceptance so we should do
too for the time being.
2026-06-09 18:03:55 +03:00
Uri Shaked ed26854793 refactor: rename uses_3v3 to uses_vapwr
The flag enables a second power supply (VAPWR), not necessarily 3.3V (gf180's core is already 3v3), so "uses_3v3" no longer accurately describes its purpose.
Rename it across project_info, precheck, project and shuttle, and update the validation message accordingly.

The legacy "uses_3v3" key is still accepted when reading info.yaml, so existing project configs keep working.
2026-05-31 16:18:24 +03:00
Uri Shaked d5b156e241 feat(precheck/gf180mcuD): analog template selection + pin check 2026-05-31 15:40:42 +03:00
htfab d4626aaed7 feat(precheck/gf180mcuD): add test for antenna check 2026-05-03 09:26:53 +02:00
htfab c904c49f53 feat(precheck/gf180mcuD): add antenna check 2026-05-03 09:26:53 +02:00
htfab 201d0273dc feat(precheck): add Verilog syntax check 2026-03-26 13:05:34 +01:00
htfab 34f7730b3a fix(precheck): force single-threaded mode in sky130A_mr.drc
avoids intermittent segfaults in klayout FEOL check
2026-03-12 22:48:48 +02:00
htfab 45fa89984f feat(precheck): add analog pin check for ihp-sg13g2 2026-02-21 07:16:36 +02:00
htfab d28b20433e feat(precheck): use new DRC deck for IHP
needs IHP PDK 34c00bdd15efd3406ab028896d2182236aad3aa7 (2025.11.25) or later
2026-02-17 20:50:41 +02:00
htfab 57cc5a39d6 feat(precheck): allow more customization for run_klayout() 2026-02-17 20:50:41 +02:00
Uri Shaked 88470b895b fix(precheck): disable analog pin check for ihp-sg13g2
The check currently uses hard-coded sky130A specific layer names and pin sizes.
2026-02-12 22:10:36 +02:00
Uri Shaked d9b4ee2345 feat(precheck): look for the .lef file in ../lef/ 2025-12-11 19:45:15 +02:00
Uri Shaked c813d4796a fix(precheck): adapt for new IHP def files
TopMetal1 is allowed now, and the power pins moved from Metal5 to TopMetal1.
2025-11-24 14:20:04 +02:00
kris j 9a14f318d6 feat(precheck): check if power pins have USE in definition (#139)
* feat(precheck): check if power pins have `USE` in definition

* fix: expect zero or more spaces, instead of one or more

* feat(precheck): check for missing `USE POWER`

* feat(precheck): check for missing `USE GROUND`

* feat(precheck): add simple README with link to LEF/DEF reference manual
2025-11-20 08:57:05 +02:00
Uri Shaked 5c4503072e feat(precheck): oas file support #134
replace legacy .gds.br support with .oas file support
2025-11-16 10:04:22 +02:00
htfab 67541ef759 feat(precheck): add pin_check for gf180mcuD
and also enable magic drc
2025-10-29 19:14:45 +02:00
htfab 0954014041 feat(precheck): initial gf180mcuD support 2025-10-28 21:41:02 +02:00
Uri Shaked 44d164955d fix(precheck): read the PDK name from the PDK environment variable 2025-09-29 16:16:20 +03:00
Uri Shaked 0529b699de fix(precheck): rename "sky130" to "sky130A"
Keep the tech naming consistent with the rest of tt-support-tools code
2025-09-13 20:28:54 +03:00
Uri Shaked 28fd25f684 refactor: separate tech specific code
Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
2025-09-13 20:28:48 +03:00
htfab e96fa6fc6f fix(precheck): use non-greedy regex for stripping verilog comments
as suggested by @smunaut
2025-09-01 23:28:25 +02:00
Uri Shaked 0baf1ece4b feat(precheck): IHP KLayout DRC 2025-04-16 17:56:01 +03:00
Uri Shaked fe543406d6 fix(precheck): disable power pin check for IHP
IHP provided verilog models do not have power ports, so we don't use powered netlists, and thus no need to check for power pins in the GL verilog.
2025-04-16 17:12:34 +03:00
Uri Shaked c350c2ed16 feat(precheck): initial IHP support
still missing the IHP Klayout DRC deck
2025-04-16 08:28:51 +03:00
htfab 022164a023 refactor(precheck): use gdstk.offset() in connectivity checks
as suggested by @tatzelbrumm
2025-02-17 09:16:00 +02:00
htfab 055de1f9fe fix(precheck): improve error messages for connectivity checks 2025-02-17 09:00:55 +02:00
htfab 2241597d6b feat(precheck): add extra prechecks
- no shapes outside project area
- VPWR/VGND present, VAPWR present iff uses_3v3
- no invalid layers
- cell names don't have '#' or '/'
- urpm to nwell spacing satisfies DRC
- analog pins have adjacent metal iff marked as used
2025-01-31 17:53:57 +02:00
htfabandhtfab 69b12ddf2c feat(precheck): add support for .gds.br compressed layouts (#87)
* feat(precheck): add support for .gds.br compressed layouts

* fix(precheck): adapt the test suite to changed klayout_checks() signature

---------

Co-authored-by: htfab <mpw@htamas.net>
2024-12-12 11:33:38 +02:00
htfab 8e41bfb1d9 feat(precheck): add support for 3v3 templates 2024-06-24 07:13:00 +03:00
Uri Shaked 674fdc7ef7 fix(precheck): update analog template paths 2024-06-18 14:29:40 +03:00
Uri Shaked d2d27ab36c fix(precheck): fails on projects in shuttle repository
It can't find info.yaml, since it's looking for it in the parent directory of the gds while info.yaml is in the same directory as the gds.
2024-05-07 09:01:09 +03:00
htfab 97e65e74f6 feat(precheck): add pin checks
Checks for missing or invalid pins, wrong pin dimensions or layers.
2024-05-01 00:55:53 +03:00
Uri Shaked 4b2bb6d000 feat(precheck): verify top level macro name
This issue appeared in tt06, in the following analog project: https://github.com/davidparent/tt_resistor_test/tree/fdc74c92ec0ec2b9817f0ea6823daa62f8ca5401/
2024-04-23 22:57:52 +03:00
Uri Shaked a6d2dae7aa fix(precheck): remove unused --markdown-report arg
the markdown report is always generated anyway
2024-04-21 00:18:35 +03:00
Uri Shaked 3067026096 feat(precheck): add prBoundary check
verifies that prBoundary layer exists
2024-04-21 00:17:48 +03:00
Uri Shaked f8dc00aeac feat(precheck): add zeroarea check 2024-04-20 00:36:09 +03:00
Uri Shaked 11a1c442ee feat(precheck): pin_label_purposes_overlapping_drawing check 2024-03-31 21:20:37 +03:00
htamas 18c67d9a7e feat(precheck): add warning for flattened cells
Flattened sky130 devices in analog layouts can lead to DRC errors.
They are difficult to test for, so as a heuristic we add a warning when magic DRC fails and there are no unflattened sky130 cells.
2024-02-26 08:46:49 +02:00
Uri Shaked ed28c2f373 feat(precheck): improve error reporting 2023-11-21 01:30:32 +02:00
Uri Shaked a97371e83a feat(precheck): make top module name optional
if not given, just assume the top module name is the same at the base name of the given GDS file
2023-11-20 17:06:36 +02:00
Uri Shaked 192baef100 refactor(precheck): add missing types 2023-11-20 15:13:59 +02:00
Uri Shaked 2df21d6e92 feat: precheck (#30)
perform DRC checks on GDS files submitted to Tiny Tapeout
2023-11-20 15:02:41 +02:00