TinyTapeout/tt-support-tools
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408 Commits 33 Branches 0 Tags
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Commit Graph
40 Commits
Author SHA1 Message Date
htfab 0954014041 feat(precheck): initial gf180mcuD support 2025-10-28 21:41:02 +02:00
Uri Shaked 44d164955d fix(precheck): read the PDK name from the PDK environment variable 2025-09-29 16:16:20 +03:00
Uri Shaked 0529b699de fix(precheck): rename "sky130" to "sky130A" 
Keep the tech naming consistent with the rest of tt-support-tools code
 2025-09-13 20:28:54 +03:00
Uri Shaked 28fd25f684 refactor: separate tech specific code 
Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
 2025-09-13 20:28:48 +03:00
Uri Shaked 278718ca12 chore: update efabless -> chipfoundry 2025-09-08 15:44:33 +03:00
htfab e96fa6fc6f fix(precheck): use non-greedy regex for stripping verilog comments 
as suggested by @smunaut
 2025-09-01 23:28:25 +02:00
Uri Shaked bebe93d93b fix(precheck): add HeatRes.drawing to list of valid IHP SG13G2 layers 2025-05-09 22:26:37 +03:00
Uri Shaked 0baf1ece4b feat(precheck): IHP KLayout DRC 2025-04-16 17:56:01 +03:00
Uri Shaked fe543406d6 fix(precheck): disable power pin check for IHP 
IHP provided verilog models do not have power ports, so we don't use powered netlists, and thus no need to check for power pins in the GL verilog.
 2025-04-16 17:12:34 +03:00
Uri Shaked 746789020e fix(precheck): update valid list of IHP SG13G2 layers 
List given by @smunaut
 2025-04-16 16:58:45 +03:00
Uri Shaked c350c2ed16 feat(precheck): initial IHP support 
still missing the IHP Klayout DRC deck
 2025-04-16 08:28:51 +03:00
htfab 022164a023 refactor(precheck): use gdstk.offset() in connectivity checks 
as suggested by @tatzelbrumm
 2025-02-17 09:16:00 +02:00
htfab 055de1f9fe fix(precheck): improve error messages for connectivity checks 2025-02-17 09:00:55 +02:00
htfab 2241597d6b feat(precheck): add extra prechecks 
- no shapes outside project area
- VPWR/VGND present, VAPWR present iff uses_3v3
- no invalid layers
- cell names don't have '#' or '/'
- urpm to nwell spacing satisfies DRC
- analog pins have adjacent metal iff marked as used
 2025-01-31 17:53:57 +02:00
htfabandhtfab 69b12ddf2c feat(precheck): add support for .gds.br compressed layouts (#87) 
* feat(precheck): add support for .gds.br compressed layouts

* fix(precheck): adapt the test suite to changed klayout_checks() signature

---------

Co-authored-by: htfab <mpw@htamas.net>
 2024-12-12 11:33:38 +02:00
Uri Shaked 96f3577cad chore(precheck): update klayout DRC deck 
following efabless/mpw_precheck#289
 2024-09-11 23:39:59 +03:00
htfab 8e41bfb1d9 feat(precheck): add support for 3v3 templates 2024-06-24 07:13:00 +03:00
Uri Shaked 674fdc7ef7 fix(precheck): update analog template paths 2024-06-18 14:29:40 +03:00
htfab 58dc0db1c1 fix: resolve version conflicts gdstk<->numpy & openlane2<->klayout 2024-06-17 08:47:46 +03:00
htfab f56fdf7cbe feat(test-precheck): support compound ports 2024-05-28 22:52:28 +03:00
htfab 12621b9a14 feat(precheck): combine rectangles within the same port 2024-05-28 22:52:28 +03:00
htfab 68e6da5b9f fix(precheck): typo 2024-05-08 20:08:10 +03:00
htfab 96bfcce676 feat(precheck): add testcase for overlapping pins 2024-05-08 20:08:10 +03:00
htfab 41b9907da4 feat(precheck): extend error message for overlapping pins 2024-05-08 20:08:10 +03:00
htfab 39162225ce feat(precheck): fail on overlapping pins 2024-05-08 20:08:10 +03:00
Uri Shaked d2d27ab36c fix(precheck): fails on projects in shuttle repository 
It can't find info.yaml, since it's looking for it in the parent directory of the gds while info.yaml is in the same directory as the gds.
 2024-05-07 09:01:09 +03:00
htfab 64bf6626f9 fix(precheck): make errors more descriptive 2024-05-01 08:54:11 +03:00
htfab 97e65e74f6 feat(precheck): add pin checks 
Checks for missing or invalid pins, wrong pin dimensions or layers.
 2024-05-01 00:55:53 +03:00
Uri Shaked 4b2bb6d000 feat(precheck): verify top level macro name 
This issue appeared in tt06, in the following analog project: https://github.com/davidparent/tt_resistor_test/tree/fdc74c92ec0ec2b9817f0ea6823daa62f8ca5401/
 2024-04-23 22:57:52 +03:00
Uri Shaked a6d2dae7aa fix(precheck): remove unused --markdown-report arg 
the markdown report is always generated anyway
 2024-04-21 00:18:35 +03:00
Uri Shaked 3067026096 feat(precheck): add prBoundary check 
verifies that prBoundary layer exists
 2024-04-21 00:17:48 +03:00
Uri Shaked f8dc00aeac feat(precheck): add zeroarea check 2024-04-20 00:36:09 +03:00
Uri Shaked eed8309348 chore(precheck): update klayout DRC rules 
following efabless/mpw_precheck#271
 2024-04-16 22:39:54 +03:00
Uri Shaked b544d27db7 fix(precheck): bump klayout dependency 
See KLayout/klayout#1670 for details
 2024-04-01 21:43:25 +03:00
Uri Shaked 11a1c442ee feat(precheck): pin_label_purposes_overlapping_drawing check 2024-03-31 21:20:37 +03:00
htamas 18c67d9a7e feat(precheck): add warning for flattened cells 
Flattened sky130 devices in analog layouts can lead to DRC errors.
They are difficult to test for, so as a heuristic we add a warning when magic DRC fails and there are no unflattened sky130 cells.
 2024-02-26 08:46:49 +02:00
Uri Shaked ed28c2f373 feat(precheck): improve error reporting 2023-11-21 01:30:32 +02:00
Uri Shaked a97371e83a feat(precheck): make top module name optional 
if not given, just assume the top module name is the same at the base name of the given GDS file
 2023-11-20 17:06:36 +02:00
Uri Shaked 192baef100 refactor(precheck): add missing types 2023-11-20 15:13:59 +02:00
Uri Shaked 2df21d6e92 feat: precheck (#30) 
perform DRC checks on GDS files submitted to Tiny Tapeout
 2023-11-20 15:02:41 +02:00