TinyTapeout/tt-support-tools
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Author SHA1 Message Date
matt venn 65034f9c5e docs(datasheet): update CREDITS.md 2024-05-02 15:34:35 +03:00
Uri Shaked 0c171af9b4 feat(fpga): read seed / target frequency from environment 
Read the values from TT_FPGA_SEED / TT_FPGA_FREQ, and default to 12 MHz frequency.
 2024-05-01 23:47:35 +03:00
Uri Shaked b6ec741349 feat(fpga): initial implementation 
Adds a new `tt_tool.py --create-fpga-bitstream` flag that creates a TT Sim FPGA bitstream from the user's project.
 2024-05-01 23:13:21 +03:00
htfab 64bf6626f9 fix(precheck): make errors more descriptive 2024-05-01 08:54:11 +03:00
Uri Shaked 81bffaf9d6 fix(datasheet): update website index header for TT07 2024-05-01 01:25:21 +03:00
Matt Venn 2beb1e67fc docs(credits): remove Aisler 2024-05-01 01:19:31 +03:00
Matt Venn fa59d328a5 docs: update pinout diagram (tt-qfn-64.svg) 2024-05-01 01:18:38 +03:00
htfab 97e65e74f6 feat(precheck): add pin checks 
Checks for missing or invalid pins, wrong pin dimensions or layers.
 2024-05-01 00:55:53 +03:00
Uri Shaked 51e5747c09 fix(tt_tool): analog project can have up to 6 analog pins 2024-04-27 22:30:43 +03:00
Uri Shaked 60c8ff8b8e fix(configure): update synth stats paths for tt06 2024-04-26 12:23:38 +03:00
Uri Shaked 4b2bb6d000 feat(precheck): verify top level macro name 
This issue appeared in tt06, in the following analog project: https://github.com/davidparent/tt_resistor_test/tree/fdc74c92ec0ec2b9817f0ea6823daa62f8ca5401/
 2024-04-23 22:57:52 +03:00
Uri Shaked 793d01ab13 feat(tt_tool): improve "pinout" section validation 
- Verify that the user filled the pinout (at least one pin description)
- Disallow unrecognized keys
 2024-04-23 00:10:44 +03:00
Uri Shaked 730fb02726 fix(website): images missing from website 
TinyTapeout/tinytapeout_www#84
 2024-04-22 00:12:20 +03:00
Uri Shaked a6d2dae7aa fix(precheck): remove unused --markdown-report arg 
the markdown report is always generated anyway
 2024-04-21 00:18:35 +03:00
Uri Shaked 3067026096 feat(precheck): add prBoundary check 
verifies that prBoundary layer exists
 2024-04-21 00:17:48 +03:00
Uri Shaked ef33610c61 feat: update analog templates for tt07 
make the analog pins wider - 0.9um instead of 0.6 um
 2024-04-20 13:39:53 +03:00
Uri Shaked 1f66d890ef fix(configure): project loading broken 2024-04-20 01:06:04 +03:00
Uri Shaked f8dc00aeac feat(precheck): add zeroarea check 2024-04-20 00:36:09 +03:00
Uri Shaked bd22f82b1b fix(configure): unhappy types 2024-04-20 00:26:49 +03:00
Uri Shaked 7f56a586c0 feat(configure): support for loading only a subset of the projects 
specified by the `TT_ONLY_PROJECTS` environment variable, e.g.:

```bash
TT_ONLY_PROJECTS="tt_um_chip_rom,tt_um_factory_test"
```
 2024-04-19 17:39:16 +03:00
Uri Shaked c74b14ac00 fix(datasheet): don't escape latex in user docs (info.md) 2024-04-17 21:28:47 +03:00
htfab bc500a3a56 fix(docs): remove text labels from subcells in png 2024-04-17 14:29:49 +03:00
Uri Shaked eed8309348 chore(precheck): update klayout DRC rules 
following efabless/mpw_precheck#271
 2024-04-16 22:39:54 +03:00
Uri Shaked d5153c3f22 fix(tt_tool): clock issue warnings break with custom openlane configs 
they break when some of the steps are disabled, e.g. https://github.com/iic-jku/jku-tt06-tdc-v2/
 2024-04-13 20:31:27 +02:00
Clive Chan f910ae51f9 Bump gdstk to work for Apple Silicon 2024-04-13 20:04:34 +02:00
Uri Shaked d9a6d6206d fix(datasheet): broken images 2024-04-11 15:14:31 +03:00
Uri Shaked 9c7ebcb731 feat(tt_tool): display clock issue warnings #34 2024-04-08 15:10:47 +03:00
Uri Shaked 16fb26f5e6 fix(datasheet): images missing #32 2024-04-08 15:04:28 +03:00
Uri Shaked 1ebe1ef29b fix(configure): correct project type in shuttle_index.md for analog projects 
was "HDL", should be "Analog"
 2024-04-06 14:51:48 +03:00
Uri Shaked ef272636b7 ci(test-precheck): update action dependencies 2024-04-05 11:50:00 +03:00
Uri Shaked b544d27db7 fix(precheck): bump klayout dependency 
See KLayout/klayout#1670 for details
 2024-04-01 21:43:25 +03:00
Uri Shaked 11a1c442ee feat(precheck): pin_label_purposes_overlapping_drawing check 2024-03-31 21:20:37 +03:00
Uri Shaked ca190609c6 fix: pass yosys commands through an environment variable 
should be safer than passing them on shell commandline
 2024-03-30 01:32:08 +03:00
Uri Shaked 1e052887a2 fix: yowasp-yosys chokes on complex verilog modules 
reproduces with https://github.com/Lucaz97/tt06_RNG2

as a workaround, we first try to read the first verilog source file, and only if we can't find the top level verilog module there, we read the rest of the files.
 2024-03-30 01:12:06 +03:00
Uri Shaked e3fac0ab40 feat: "layout" section in shuttle_index 
contains information about the type each each mux (analog / digital)
 2024-03-21 23:36:50 +02:00
Uri Shaked a97e6b03b6 feat(configure): copy analog switch (asw) macro 2024-03-21 18:09:32 +02:00
Uri Shaked 316141d73a fix(ci): mypy check fails 
upgrade python from 3.9 to 3.11
 2024-03-19 11:47:36 +02:00
Uri Shaked ef5539b7a0 feat: new format for shuttle_index 
1. Bump "version" to 3
2. Rename "shuttle" to "name"
2. Rename "mux" to "projects", and turn it from a dict into a list
3. Project entries: add "address" (which was previously the key of the "mux" dict), remove "features" and add optional "analog_pins" with a list of analog pin assignment.
 2024-03-18 01:16:22 +02:00
Uri Shaked b1a2a3bb98 feat(configure): initial support for analog module placement 2024-03-16 23:26:56 +02:00
Uri Shaked 8cd1ef73cb ci: upgrade volare action 2024-03-16 23:17:47 +02:00
Uri Shaked 51bb1d0bf5 fix: don't generate pg_vdd property in tt-multiplexer's modules.yaml 
All user macros are now power gated by default
 2024-03-13 23:03:07 +02:00
Uri Shaked 12c79b065c fix(tt_tool): broken PNG render for openlane projects 2024-03-01 15:43:45 +02:00
Uri Shaked 49b8e8724c feat(tt_tool): support for specifying custom GDS file for PNG render 
tinytapeout/tt-gds-action#12
 2024-02-29 22:38:35 +02:00
htamas 18c67d9a7e feat(precheck): add warning for flattened cells 
Flattened sky130 devices in analog layouts can lead to DRC errors.
They are difficult to test for, so as a heuristic we add a warning when magic DRC fails and there are no unflattened sky130 cells.
 2024-02-26 08:46:49 +02:00
Uri Shaked f6fae279c1 fix: projects that manually instantiate standard cells fail 
remove an assestion that causes these projects to fail

fix #31
 2024-02-21 15:31:28 +02:00
Uri Shaked e8c5040dc5 fix(tt_tool): fails on non-analog projects 2024-02-01 13:06:19 +02:00
Uri Shaked 7126553f3c feat: analog project support 
handle ua[7:0] pins in analog modules
 2024-01-30 21:43:04 +02:00
Uri Shaked 65a2a24087 feat: tt_block def file for analog projects 
They add eight analog pins (`ua[7:0]`) in addition to the standard Tiny Tapeout digital pins.
 2024-01-30 17:28:10 +02:00
Uri Shaked ad9184ec8a chore: remove start_date from config.yaml 
we don't use it
 2024-01-29 10:41:05 +02:00
Uri Shaked 67529a8120 feat(tt_tool): require that clock_hz be an integer 2024-01-23 14:49:41 +02:00