Commit Graph
4 Commits
Author SHA1 Message Date
Uri Shaked 8f2ff888d6 style(rom): format verilog code with verible 2025-02-02 10:48:37 +02:00
Uri Shaked 17e08942b2 feat(rom): add Magic and CRC32 fields 2024-05-29 16:18:08 +03:00
Uri Shaked 23da39ba14 feat: include chip ROM when running in verification mode (--test) 2023-09-11 15:35:24 +03:00
Uri Shaked cadbfbcd25 feat: Chip ROM auto generation with OpenLane 2
So we can generate the ROM while building the shuttle's GDS
2023-09-10 20:17:58 +03:00