TinyTapeout/tt-support-tools
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Author SHA1 Message Date
Uri Shaked 562ebd4f93 feat: update user module def files 
to support tt-multiplexer with power gating. built from tt-multiplexer commit dfbcff452131ea42631f9e358687c22776daffdc
 2023-10-12 22:37:09 +03:00
Uri Shaked 82720e4b84 feat: support for skipping designs 
by specifying ` "skip": true ` in commit_id.json
 2023-10-12 22:34:13 +03:00
Uri Shaked e807454c33 fix: copy powered netlist when building tt_top 
the new power gated tt-multiplexer requires powered netlist for the included macros.
 2023-10-12 19:08:48 +03:00
Uri Shaked 462004f9e0 feat: generate gl includes for user projects 
This enables running GL tests on the final GL netlist of the actual chip
 2023-10-01 23:27:36 +03:00
Uri Shaked 5925525982 fix(datasheet): fails when "bidirectional" is empty 
e.g.

```yaml
documentation:
  ...

# A description of what the inputs do (e.g. red button, SPI CLK, SPI MOSI, etc).
  inputs:
    - sclrn
    - ser
    - rck
    - srck
    - G
# A description of what the outputs do (e.g. status LED, SPI MISO, etc)
  outputs:
    - q[0]
    - q[1]
    - q[2]
    - q[3]
    - q[4]
    - q[5]
    - q[6]
    - q[7]
# A description of what the bidirectional I/O pins do (e.g. I2C SDA, I2C SCL, etc)
  bidirectional:

```
 2023-09-30 07:58:45 +03:00
Uri Shaked 2387160df7 ci: lint job name 2023-09-21 22:31:37 +03:00
Uri Shaked aa8f760375 style: fix lint errors + reformat source with black 2023-09-21 22:30:52 +03:00
Uri Shaked 7d48aab542 ci: add link-check action 2023-09-21 22:25:05 +03:00
Uri Shaked 5725713cbd chore: set up flake8, isort and black with pre-commit 2023-09-21 22:21:59 +03:00
Uri Shaked 3f8a47659c fix: path to openlane2 yosys synth log 2023-09-21 08:17:15 +03:00
Uri Shaked 77fcb0c98f ci: fix broken mypy action 
install required type packages
 2023-09-19 20:55:52 +03:00
Uri Shaked da14cd0502 ci: github action to check python types 2023-09-19 20:44:43 +03:00
Uri Shaked ff0eea8794 refactor: add more types 2023-09-19 20:42:47 +03:00
Uri Shaked 3b469b9488 refactor: add types to project.py 2023-09-19 19:52:47 +03:00
Uri Shaked 8df6312688 refactor: add types to git_utils 2023-09-19 19:07:34 +03:00
Anton MaurovicandAnton Maurovic 76835903c0 peftGDS=>PNG render improvement for GitHub Actions and local (#28) 
* Add --create-png-preview option; more-robust GDS to PNG rendering for GHA

* Minor update to --create-png-preview

* Change --create-png-preview to just be a --create-png replacement

* Minor --create-png improvement

---------

Co-authored-by: Anton Maurovic <algo@foogle.com>
 2023-09-19 07:27:59 +03:00
Uri Shaked e981222768 feat: add commit_date field to shuttle_index.json 
The commit date provides an easy method to compare two shuttle_index.json files and detect which of the files relates to a newer commit. This enables us to prevent a situation where an earlier shuttle_index overrides a later one.
 2023-09-14 15:13:59 +03:00
Uri Shaked 000002721f docs: add qfn-64 pinout 2023-09-14 13:39:32 +03:00
Uri Shaked b03ea5ab2e feat: 3x2 tile size support 2023-09-13 13:58:21 +03:00
matt venn 46e58b675f Update CREDITS.md 
add Mitch
 2023-09-12 18:30:08 +02:00
Matt Venn b5e5bc99e8 Merge branch 'tt05' of https://github.com/TinyTapeout/tt-support-tools into tt05 2023-09-11 15:33:25 +02:00
Matt Venn 37c18a964e update logo and include projects that have missing pins in the datasheet 2023-09-11 15:33:06 +02:00
Uri Shaked 23da39ba14 feat: include chip ROM when running in verification mode (--test) 2023-09-11 15:35:24 +03:00
Uri Shaked b02cc19e78 fix: shuttle config fails as tt_um_chip_rom verilog is missing 
The Chip ROM is now auto generated, so the GL verilog only exists after we configure the shuttle
 2023-09-10 20:23:48 +03:00
Uri Shaked cadbfbcd25 feat: Chip ROM auto generation with OpenLane 2 
So we can generate the ROM while building the shuttle's GDS
 2023-09-10 20:17:58 +03:00
Uri Shaked 5e863fc333 fix: final GDS file name no longer includes ".magic" 
The final GDS file name has changed in recent OpenLane2 and is now {module}.gds instead of {module}.magic.gds.
 2023-09-10 12:56:17 +03:00
Uri Shaked acb6b6b4c3 refactor: caravel.py -> shuttle.py 2023-09-09 21:45:01 +03:00
Uri Shaked cc1b5806b2 fix: correct project gl path when running configure.py 2023-09-09 21:39:08 +03:00
Uri Shaked 340b747e4a Merge pull request #26 from htfab/tt04 
Allow svg and pdf images in the datasheet
 2023-09-09 20:37:58 +03:00
Boundary Effect 8717325500 feat(datasheet): allow pdf images 2023-09-09 00:11:51 +02:00
Boundary Effect 389d181cbb feat(datasheet): allow svg images 2023-09-09 00:10:44 +02:00
Uri Shaked 1da6923f8c fix: wrong extension for .lef file in efabless submission artifact 2023-09-08 23:59:38 +03:00
Uri Shaked e7ea59f4d0 feat(datasheet): roses are red, links are blue 
add color to links so they stand out
 2023-09-07 21:36:46 +03:00
Uri Shaked 010cebe7d6 fix(datasheet): remove outdated STA / Verification sections 2023-09-07 20:53:56 +03:00
Uri Shaked af58bde8be fix: missing commit_id.json in openlane2 projects 2023-09-06 19:36:15 +03:00
Uri Shaked fd29f74a1a feat: initial support for openlane2 user projects 2023-09-06 18:04:02 +03:00
Uri Shaked da5f3cb1f8 fix(datasheet): broken links to git / extra docs 2023-09-06 10:02:13 +03:00
Uri Shaked 09c57b7938 fix(datasheet): blackslash characters still break the datasheet 
applied a bruteforce workaround (replace every backslash with `\mbox{\\textbackslash}`) so we can still get the datasheet generated
 2023-09-06 10:02:08 +03:00
Uri Shaked 3f55bd709a feat: copy spef / gl netlists of tt_ctrl/tt_mux 2023-09-05 12:23:37 +03:00
Uri Shaked ae0f2483ba fix(datasheet): backslash characters in project description break the datasheet 
e.g. the "description" field of the following info.yaml would break the datasheet generation:

```yaml
documentation:

  author:       "Sarthak Raheja and Bittu N"      # Your name
  title:        "Simple Piano"      # Project title
  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc

  # Short description of what your project does
  description:  |
    The input clock is divided into a series of frequencies to mimic a piano having only 12 keys of one octave. User can choose from a choice of 3-5 octaves. Additionally, few pre-defined tunes have been included using RTTTL logic\n
```
 2023-09-05 10:13:21 +03:00
Uri Shaked dac3f4a0a4 fix: disable ROM vmem file generation 
it breaks the tiny tapeout staging repo, and we don't use the ROM vmem file yet anyway (the ROM content is hardened as part of the tt-chip-rom repo)
 2023-08-06 18:05:39 +03:00
Uri Shaked 64d21511b0 Merge pull request #24 from marnovandermaas/fix_documentation_margin 
Increase the bottom margin to show page number
 2023-08-01 18:21:20 +03:00
Marno van der Maas e0aca0d5c8 Increase the bottom margin to show page number 
Previously with the 2cm bottom margin, the documentation was cutting off
the page number about half way, so I increase the bottom margin from 2
to 3cm.
 2023-08-01 16:08:29 +01:00
Uri Shaked 24c15519e8 fix(datasheet): broken user module pictures / diagrams 
close #22
 2023-07-31 09:02:16 +03:00
Uri Shaked 1aa125fdd5 fix(datasheet): broken images, replace scanchain info with mux 
- fix some of the broken images
- render the mux's info doc in place of the scanchain doc
 2023-07-30 23:09:31 +03:00
Uri Shaked 7842384b6a fix(datasheet): markdown headings break the datasheet 
close #23
 2023-07-30 22:21:00 +03:00
Uri Shaked 6034820170 fix(datasheet): use shuttle name from config 
also, dynamically figure out the repo URL (instead of using an hardcoded value)
 2023-07-30 09:40:16 +03:00
Uri Shaked e56503e9c3 docs: remove outdated hardening doc 2023-07-29 23:00:51 +03:00
Uri Shaked 769cc65983 feat(datasheet): include mux addresses 2023-07-29 22:48:53 +03:00
Uri Shaked c83c2cd3c7 feat(datasheet): add bidrectional pins 
close #11
 2023-07-29 22:28:15 +03:00