Commit Graph
24 Commits
Author SHA1 Message Date
Uri Shaked d1bbd34d95 feat(precheck/gf180mcuD): update to latest PDK 2026-06-14 20:23:49 +03:00
Uri Shaked 50998ec8f8 feat(precheck/gf180mcuD): run KLayout DRC via PDK run_drc.py
- Density related rules skipped (irrelevant for user projects)
- Add docopt dependecy (required by the PDK's run_drc.py)
2026-06-14 16:50:19 +03:00
Uri Shaked ed26854793 refactor: rename uses_3v3 to uses_vapwr
The flag enables a second power supply (VAPWR), not necessarily 3.3V (gf180's core is already 3v3), so "uses_3v3" no longer accurately describes its purpose.
Rename it across project_info, precheck, project and shuttle, and update the validation message accordingly.

The legacy "uses_3v3" key is still accepted when reading info.yaml, so existing project configs keep working.
2026-05-31 16:18:24 +03:00
htfab d4626aaed7 feat(precheck/gf180mcuD): add test for antenna check 2026-05-03 09:26:53 +02:00
htfab 201d0273dc feat(precheck): add Verilog syntax check 2026-03-26 13:05:34 +01:00
kris j 9a14f318d6 feat(precheck): check if power pins have USE in definition (#139)
* feat(precheck): check if power pins have `USE` in definition

* fix: expect zero or more spaces, instead of one or more

* feat(precheck): check for missing `USE POWER`

* feat(precheck): check for missing `USE GROUND`

* feat(precheck): add simple README with link to LEF/DEF reference manual
2025-11-20 08:57:05 +02:00
Uri Shaked 0529b699de fix(precheck): rename "sky130" to "sky130A"
Keep the tech naming consistent with the rest of tt-support-tools code
2025-09-13 20:28:54 +03:00
Uri Shaked 28fd25f684 refactor: separate tech specific code
Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
2025-09-13 20:28:48 +03:00
Uri Shaked c350c2ed16 feat(precheck): initial IHP support
still missing the IHP Klayout DRC deck
2025-04-16 08:28:51 +03:00
htfab 055de1f9fe fix(precheck): improve error messages for connectivity checks 2025-02-17 09:00:55 +02:00
htfab 2241597d6b feat(precheck): add extra prechecks
- no shapes outside project area
- VPWR/VGND present, VAPWR present iff uses_3v3
- no invalid layers
- cell names don't have '#' or '/'
- urpm to nwell spacing satisfies DRC
- analog pins have adjacent metal iff marked as used
2025-01-31 17:53:57 +02:00
htfabandhtfab 69b12ddf2c feat(precheck): add support for .gds.br compressed layouts (#87)
* feat(precheck): add support for .gds.br compressed layouts

* fix(precheck): adapt the test suite to changed klayout_checks() signature

---------

Co-authored-by: htfab <mpw@htamas.net>
2024-12-12 11:33:38 +02:00
htfab 8e41bfb1d9 feat(precheck): add support for 3v3 templates 2024-06-24 07:13:00 +03:00
Uri Shaked 674fdc7ef7 fix(precheck): update analog template paths 2024-06-18 14:29:40 +03:00
htfab f56fdf7cbe feat(test-precheck): support compound ports 2024-05-28 22:52:28 +03:00
htfab 68e6da5b9f fix(precheck): typo 2024-05-08 20:08:10 +03:00
htfab 96bfcce676 feat(precheck): add testcase for overlapping pins 2024-05-08 20:08:10 +03:00
htfab 97e65e74f6 feat(precheck): add pin checks
Checks for missing or invalid pins, wrong pin dimensions or layers.
2024-05-01 00:55:53 +03:00
Uri Shaked 4b2bb6d000 feat(precheck): verify top level macro name
This issue appeared in tt06, in the following analog project: https://github.com/davidparent/tt_resistor_test/tree/fdc74c92ec0ec2b9817f0ea6823daa62f8ca5401/
2024-04-23 22:57:52 +03:00
Uri Shaked 3067026096 feat(precheck): add prBoundary check
verifies that prBoundary layer exists
2024-04-21 00:17:48 +03:00
Uri Shaked f8dc00aeac feat(precheck): add zeroarea check 2024-04-20 00:36:09 +03:00
Uri Shaked ed28c2f373 feat(precheck): improve error reporting 2023-11-21 01:30:32 +02:00
Uri Shaked 192baef100 refactor(precheck): add missing types 2023-11-20 15:13:59 +02:00
Uri Shaked 2df21d6e92 feat: precheck (#30)
perform DRC checks on GDS files submitted to Tiny Tapeout
2023-11-20 15:02:41 +02:00