Commit Graph
64 Commits
Author SHA1 Message Date
htfab 64bf6626f9 fix(precheck): make errors more descriptive 2024-05-01 08:54:11 +03:00
htfab 97e65e74f6 feat(precheck): add pin checks
Checks for missing or invalid pins, wrong pin dimensions or layers.
2024-05-01 00:55:53 +03:00
Uri Shaked 4b2bb6d000 feat(precheck): verify top level macro name
This issue appeared in tt06, in the following analog project: https://github.com/davidparent/tt_resistor_test/tree/fdc74c92ec0ec2b9817f0ea6823daa62f8ca5401/
2024-04-23 22:57:52 +03:00
Uri Shaked a6d2dae7aa fix(precheck): remove unused --markdown-report arg
the markdown report is always generated anyway
2024-04-21 00:18:35 +03:00
Uri Shaked 3067026096 feat(precheck): add prBoundary check
verifies that prBoundary layer exists
2024-04-21 00:17:48 +03:00
Uri Shaked f8dc00aeac feat(precheck): add zeroarea check 2024-04-20 00:36:09 +03:00
Uri Shaked eed8309348 chore(precheck): update klayout DRC rules
following efabless/mpw_precheck#271
2024-04-16 22:39:54 +03:00
Uri Shaked b544d27db7 fix(precheck): bump klayout dependency
See KLayout/klayout#1670 for details
2024-04-01 21:43:25 +03:00
Uri Shaked 11a1c442ee feat(precheck): pin_label_purposes_overlapping_drawing check 2024-03-31 21:20:37 +03:00
htamas 18c67d9a7e feat(precheck): add warning for flattened cells
Flattened sky130 devices in analog layouts can lead to DRC errors.
They are difficult to test for, so as a heuristic we add a warning when magic DRC fails and there are no unflattened sky130 cells.
2024-02-26 08:46:49 +02:00
Uri Shaked ed28c2f373 feat(precheck): improve error reporting 2023-11-21 01:30:32 +02:00
Uri Shaked a97371e83a feat(precheck): make top module name optional
if not given, just assume the top module name is the same at the base name of the given GDS file
2023-11-20 17:06:36 +02:00
Uri Shaked 192baef100 refactor(precheck): add missing types 2023-11-20 15:13:59 +02:00
Uri Shaked 2df21d6e92 feat: precheck (#30)
perform DRC checks on GDS files submitted to Tiny Tapeout
2023-11-20 15:02:41 +02:00