{
  "DESIGN_NAME": "tt_um_chip_rom",
  "VERILOG_FILES": "dir::tt_um_chip_rom.v",

  "FP_SIZING": "absolute",
  "DIE_AREA": [0, 0, 212.16, 154.98],
  "FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../ihp/def/tt_block_1x1.def",

  "FP_IO_HLENGTH": 2,
  "FP_IO_VLENGTH": 2,

  "//": "period is in ns, so 20ns == 50mHz",
  "CLOCK_PERIOD": 20,
  "CLOCK_PORT": "clk",

  "//": "don't use power rings or TopMetal",
  "DESIGN_IS_CORE": false,
  "RT_MAX_LAYER": "Metal5",

  "//": "save some time",
  "RUN_KLAYOUT_XOR": false,

  "//": "reduce wasted space",
  "TOP_MARGIN_MULT": 1,
  "BOTTOM_MARGIN_MULT": 1,
  "LEFT_MARGIN_MULT": 6,
  "RIGHT_MARGIN_MULT": 6
}