{
  "DESIGN_NAME": "tt_um_chip_rom",
  "VERILOG_FILES": "dir::tt_um_chip_rom.v",

  "FP_SIZING": "absolute",

  "FP_IO_HLENGTH": 2,
  "FP_IO_VLENGTH": 2,

  "//": "period is in ns, so 20ns == 50mHz",
  "CLOCK_PERIOD": 20,
  "CLOCK_PORT": "clk",

  "//": "don't use power rings",
  "DESIGN_IS_CORE": false,

  "//": "save some time",
  "RUN_KLAYOUT_XOR": false,

  "//": "reduce wasted space",
  "TOP_MARGIN_MULT": 1,
  "BOTTOM_MARGIN_MULT": 1,
  "LEFT_MARGIN_MULT": 6,
  "RIGHT_MARGIN_MULT": 6,

  "pdk::sky130A": {
    "DIE_AREA": [0, 0, 161.0, 111.52],
    "FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../tech/sky130A/def/tt_block_1x1_pg.def",
    "RT_MAX_LAYER": "met4"
  },

  "pdk::gf180mcuD": {
    "DIE_AREA": [0, 0, 346.64, 160.72],
    "FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../tech/gf180mcuD/def/tt_block_1x1_pgvdd.def",
    "RT_MAX_LAYER": "Metal4",
    "RUN_KLAYOUT_DRC": false
  },

  "pdk::ihp-sg13g2": {
    "DIE_AREA": [0, 0, 202.08, 154.98],
    "FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../tech/ihp-sg13g2/def/tt_block_1x1_pgvdd.def",
    "RT_MAX_LAYER": "Metal5"
  },

  "pdk::ihp-sg13cmos5l": {
    "DIE_AREA": [0, 0, 202.08, 154.98],
    "FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../tech/ihp-sg13cmos5l/def/tt_block_1x1_pgvdd.def",
    "RT_MAX_LAYER": "Metal4"
  }
}