mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
Uri Shaked
ed26854793
The flag enables a second power supply (VAPWR), not necessarily 3.3V (gf180's core is already 3v3), so "uses_3v3" no longer accurately describes its purpose. Rename it across project_info, precheck, project and shuttle, and update the validation message accordingly. The legacy "uses_3v3" key is still accepted when reading info.yaml, so existing project configs keep working.
198 lines
12 KiB
Python
198 lines
12 KiB
Python
tech_names = ["sky130A", "ihp-sg13g2", "gf180mcuD"]
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# fmt: off
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valid_layers_sky130A = [
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'cldntm.mask', 'ldntm.drawing', 'cncm.mask', 'ctunm.mask', 'cnwm.mask', 'cnsm.mask', 'cfom.drawing', 'cfom.maskAdd',
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'cfom.maskDrop', 'cfom.waffleDrop', 'cfom.mask', 'clvtnm.mask', 'cntm.drawing', 'cntm.mask', 'cp1m.mask',
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'cnsdm.drawing', 'cnsdm.maskAdd', 'cnsdm.maskDrop', 'cnsdm.mask', 'cpsdm.drawing', 'cpsdm.maskAdd', 'cpsdm.maskDrop',
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'cpsdm.mask', 'cp1m.waffleDrop', 'cp1m.maskDrop', 'cp1m.maskAdd', 'cmm3.mask', 'cctm1.mask', 'cmm1.mask', 'cpdm.mask',
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'chvntm.drawing', 'chvntm.mask', 'cviam.mask', 'cmm2.mask', 'clicm1.mask', 'cviam2.mask', 'pwelliso.label',
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'pwelliso.pin', 'cnpc.drawing', 'clvom.drawing', 'clvom.mask', 'cdnm.mask', 'cnpc.mask', 'cviam3.mask', 'cmm4.mask',
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'crpm.maskDrop', 'crpm.maskAdd', 'crpm.drawing', 'cli1m.mask', 'cviam4.mask', 'cmm5.mask', 'nsm.drawing',
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'cmm1.waffleDrop', 'nwell.label', 'pwell.res', 'pwell.cut', 'nwell.pin', 'dnwell.drawing', 'nwell.drawing',
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'pwell.drawing', 'pwell.label', 'diff.hv', 'diff.res', 'diff.cut', 'diff.drawing', 'tap.drawing', 'poly.boundary',
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'poly.label', 'poly.gate', 'poly.res', 'poly.cut', 'poly.short', 'poly.pin', 'poly.drawing', 'poly.net', 'poly.probe',
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'licon1.net', 'licon1.drawing', 'licon1.boundary', 'poly.model', 'li1.boundary', 'li1.label', 'li1.blockage',
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'li1.short', 'li1.pin', 'li1.drawing', 'li1.net', 'li1.probe', 'mcon.net', 'mcon.drawing', 'mcon.boundary',
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'met1.boundary', 'met1.label', 'met1.blockage', 'met1.short', 'met1.pin', 'met1.drawing', 'met1.net', 'met1.probe',
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'via.net', 'via.drawing', 'via.boundary', 'met1.psa1', 'met1.psa2', 'met1.psa3', 'met1.psa4', 'met1.psa5', 'met1.psa6',
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'met2.boundary', 'met2.label', 'met2.blockage', 'met2.short', 'met2.pin', 'met2.drawing', 'met2.net', 'met2.probe',
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'via2.net', 'via2.drawing', 'via2.boundary', 'met2.psa1', 'met2.psa2', 'met2.psa3', 'met2.psa4', 'met2.psa5',
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'met2.psa6', 'met3.boundary', 'met3.label', 'met3.blockage', 'met3.short', 'met3.pin', 'met3.drawing', 'met3.net',
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'met3.probe', 'via3.net', 'via3.drawing', 'via3.boundary', 'met3.psa1', 'met3.psa2', 'met3.psa3', 'met3.psa4',
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'met3.psa5', 'met3.psa6', 'met4.boundary', 'met4.label', 'met4.blockage', 'met4.short', 'met4.pin', 'met4.drawing',
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'met4.net', 'met4.probe', 'via4.net', 'via4.drawing', 'via4.boundary', 'met4.psa1', 'met4.psa2', 'met4.psa3',
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'met4.psa4', 'met4.psa5', 'met4.psa6', 'met5.boundary', 'met5.label', 'met5.blockage', 'met5.short', 'met5.pin',
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'met5.drawing', 'met5.net', 'met5.probe', 'met5.psa1', 'met5.psa2', 'met5.psa3', 'met5.psa4', 'met5.psa5', 'met5.psa6',
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'rdl.label', 'rdl.res', 'rdl.cut', 'rdl.pin', 'rdl.drawing', 'vhvi.drawing', 'rdl.psa1', 'rdl.psa2', 'rdl.psa3',
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'rdl.psa4', 'rdl.psa5', 'rdl.psa6', 'hvi.drawing', 'pad.label', 'pad.pin', 'pad.drawing', 'target.drawing',
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'pmm2.drawing', 'hvtp.drawing', 'tunm.drawing', 'areaid.seal', 'areaid.core', 'areaid.frame', 'areaid.standardc',
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'areaid.sigPadDiff', 'areaid.sigPadWell', 'areaid.sigPadMetNtr', 'areaid.moduleCut', 'areaid.dieCut',
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'areaid.frameRect', 'areaid.waffleWindow', 'areaid.lowTapDensity', 'areaid.notCritSide', 'areaid.injection',
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'areaid.esd', 'padCenter.drawing', 'areaid.diode', 'areaid.rdlprobepad', 'areaid.deadZon', 'areaid.critCorner',
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'areaid.critSid', 'areaid.substrateCut', 'areaid.opcDrop', 'areaid.extendedDrain', 'areaid.lvNative', 'areaid.hvnwell',
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'areaid.analog', 'areaid.photo', 'areaid.etest', 'areaid.rfdiode', 'npn.label', 'npn.drawing', 'inductor.drawing',
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'inductor.label', 'inductor.term1', 'inductor.term2', 'inductor.term3', 'pnp.drawing', 'pnp.label', 'capacitor.drawing',
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'nwell.net', 'prune.drawing', 'pmm.drawing', 'rpm.drawing', 'conom.maskDrop', 'conom.maskAdd', 'conom.drawing',
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'conom.mask', 'capm.drawing', 'overlap.boundary', 'overlap.drawing', 'cpmm.drawing', 'ncm.drawing', 'nsdm.drawing',
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'psdm.drawing', 'npc.drawing', 'crpm.mask', 'ctunm.drawing', 'ctunm.maskAdd', 'ctunm.maskDrop', 'cncm.drawing',
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'chvtpm.mask', 'capm2.drawing', 'cpbo.mask', 'cmm2.waffleDrop', 'clicm1.maskDrop', 'clicm1.maskAdd', 'cmm3.waffleDrop',
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'cdnm.drawing', 'cdnm.maskAdd', 'cdnm.maskDrop', 'cmm4.waffleDrop', 'cmm4.maskDrop', 'cmm4.maskAdd', 'cli1m.maskDrop',
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'cli1m.maskAdd', 'cmm5.waffleDrop', 'pwell.pin', 'hvntm.drawing', 'lvtn.drawing', 'ubm.drawing', 'bump.drawing',
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'prBoundary.boundary',
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(10, 0), (11, 20), (18, 20), (22, 23), (23, 28), (25, 42), (25, 43), (25, 44), (26, 21), (26, 22), (28, 28), (33, 44),
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(34, 28), (36, 28), (38, 21), (38, 22), (41, 28), (44, 42), (44, 43), (45, 21), (45, 22), (51, 28), (56, 28), (59, 28),
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(62, 20), (62, 21), (62, 22), (65, 4), (65, 5), (65, 6), (65, 16), (65, 23), (65, 41), (65, 48), (65, 60), (66, 58),
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(67, 13), (67, 14), (67, 48), (68, 13), (68, 14), (68, 32), (68, 33), (68, 34), (68, 35), (68, 36), (68, 37), (68, 38),
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(68, 39), (68, 48), (68, 58), (69, 13), (69, 14), (69, 32), (69, 33), (69, 34), (69, 35), (69, 36), (69, 37), (69, 38),
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(69, 39), (69, 48), (69, 58), (70, 13), (70, 14), (70, 17), (70, 32), (70, 33), (70, 34), (70, 35), (70, 36), (70, 37),
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(70, 38), (70, 39), (70, 48), (71, 13), (71, 14), (71, 17), (71, 32), (71, 33), (71, 34), (71, 35), (71, 36), (71, 37),
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(71, 38), (71, 39), (71, 48), (72, 13), (72, 14), (72, 17), (72, 32), (72, 33), (72, 34), (72, 35), (72, 36), (72, 37),
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(72, 38), (72, 39), (74, 15), (74, 22), (79, 20), (83, 44), (88, 44), (89, 32), (89, 33), (89, 34), (89, 35), (89, 36),
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(89, 37), (89, 38), (89, 39), (93, 0), (94, 0), (97, 42), (97, 43), (98, 0), (98, 42), (98, 43), (98, 44), (100, 0),
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(101, 0), (101, 42), (101, 43), (101, 44), (104, 42), (104, 43), (104, 44), (105, 20), (105, 21), (105, 22), (105, 42),
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(105, 43), (105, 44), (106, 44), (107, 20), (107, 21), (107, 22), (108, 20), (108, 21), (108, 22), (109, 42), (109, 43),
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(109, 44), (112, 20), (112, 21), (112, 22), (115, 44), (117, 20), (117, 21), (117, 22), (122, 5), (124, 40), (201, 20),
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(235, 0), (235, 250), (235, 252), (236, 0),
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]
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valid_layers_ihp_sg13g2 = [
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"Substrate.drawing", "Substrate.text", "Activ.drawing", "Activ.label", "Activ.nofill", "Activ.pin", "GatPoly.drawing",
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"GatPoly.label", "GatPoly.nofill", "GatPoly.pin", "PolyRes.drawing", "PolyRes.label", "PolyRes.pin", "NWell.drawing",
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"NWell.label", "NWell.pin", "nBuLay.drawing", "nBuLay.label", "nBuLay.pin", "nBuLay.block", "PWell.block",
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"pSD.drawing", "nSD.drawing", "nSD.block", "SalBlock.drawing", "ThickGateOx.drawing", "Cont.drawing", "Metal1.drawing",
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"Metal1.label", "Metal1.nofill", "Metal1.pin", "Metal1.slit", "Metal1.text", "Metal1.res", "Via1.drawing",
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"Metal2.drawing", "Metal2.label", "Metal2.nofill", "Metal2.pin", "Metal2.slit", "Metal2.text", "Metal2.res",
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"Via2.drawing", "Via2.net", "Via2.boundary", "Metal3.drawing", "Metal3.label", "Metal3.nofill", "Metal3.pin",
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"Metal3.slit", "Metal3.text", "Metal3.res", "MIM.drawing", "Vmim.drawing", "Via3.drawing", "Metal4.drawing",
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"Metal4.label", "Metal4.nofill", "Metal4.pin", "Metal4.slit", "Metal4.text", "Metal4.res", "Via4.drawing",
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"Metal5.drawing", "Metal5.label", "Metal5.nofill", "Metal5.pin", "Metal5.slit", "Metal5.text", "Metal5.res",
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"TopVia1.drawing", "TopMetal1.drawing", "TopMetal1.label", "TopMetal1.nofill", "TopMetal1.pin", "TopMetal1.slit",
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"TopMetal1.text", "TopMetal1.res", "TopMetal2.nofill", "IND.drawing", "IND.pin", "IND.boundary", "IND.text",
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"TEXT.drawing", "Recog.drawing", "Recog.pin", "Recog.esd", "Recog.diode", "Recog.tsv", "Recog.pdiode", "Recog.mom",
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"DigiBnd.drawing", "DigiBnd.drawing0", "RES.drawing", "RES.label", "SRAM.drawing", "SRAM.label", "SRAM.boundary",
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"DigiSub.drawing", "HeatRes.drawing", "NoRCX.drawing", "NoRCX.m2m3", "NoRCX.m2m4", "NoRCX.m2m5", "NoRCX.m2tm1",
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"NoRCX.m2tm2", "NoRCX.m3m4", "NoRCX.m3m5", "NoRCX.m3tm1", "NoRCX.m3tm2", "NoRCX.m4m5", "NoRCX.m4tm1", "NoRCX.m4tm2",
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"NoRCX.m5tm1", "NoRCX.m5tm2", "NoRCX.tm1tm2", "NoRCX.m1sub", "NoRCX.m2sub", "NoRCX.m3sub", "NoRCX.m4sub", "NoRCX.m5sub",
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"NoRCX.tm1sub", "Varicap.drawing", "EXTBlock.drawing", "prBoundary.label", "prBoundary.boundary",
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"isoNWell.drawing",
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]
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valid_layers_gf180mcuD = [
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'PR_bndry', 'pass_mk', 'fail_mk', 'polygon_mk', 'NAT', 'violation_mk', 'MCELL_FEOL_MK', 'MVPSD', 'rule_txt_mk',
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'DNWELL', 'PROBE_MK', 'case_txt_mk', 'Nwell', 'COMP', 'COMP_Dummy', 'COMP_Label', 'ESD', 'ESD_MK', 'Poly2',
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'Poly2_Dummy', 'Poly2_Label', 'Pplus', 'Nplus', 'Contact', 'Metal1', 'Metal1_Slot', 'Metal1_Dummy', 'Metal1_BLK',
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'Metal1_Label', 'Via1', 'Metal2', 'Metal2_Slot', 'Metal2_Dummy', 'Metal2_BLK', 'Metal2_Label', 'Pad', 'Via2', 'Via3',
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'Via4', 'Metal3', 'Metal3_Slot', 'Metal3_Dummy', 'Metal3_BLK', 'Metal3_Label', 'Metal4', 'Metal4_Slot', 'Metal4_Dummy',
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'Metal4_BLK', 'Metal4_Label', 'SAB', 'MetalTop', 'MetalTop_Slot', 'MetalTop_Dummy', 'MetalT_BLK', 'MetalTop_Label',
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'Dualgate', 'Resistor', 'Border', 'FuseTop', 'EFUSE_MK', 'Metal5', 'Metal5_Slot', 'Metal5_Dummy', 'Metal5_BLK',
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'Metal5_Label', 'Via5', 'YMTP_MK', 'NEO_EE_MK', 'FuseWindow_D', 'LVS_RF', 'LVS_Drain', 'LVS_Source', 'SramCore',
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'RES_MK', 'Metal1_Res', 'Metal2_Res', 'Metal3_Res', 'Metal4_Res', 'Metal5_Res', 'Metal6_Res', 'NDMY', 'V5_XTOR',
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'DIODE_MK', 'MDIODE', 'CAP_MK', 'MIM_L_MK', 'LVS_BJT', 'LVS_IO', 'MTPMARK', 'HVPOLYRS', 'OPC_drc', 'PLFUSE', 'DRC_BJT',
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'DEV_WF_MK', 'Latchup_MK', 'IND_MK', 'PMNDMY', 'WELL_DIODE_MK', 'MOS_CAP_MK', 'GUARD_RING_MK', 'OTP_MK', 'ZENER',
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'UBMPPeri', 'UBMPArray', 'UBMEPlate', 'LVPWELL', 'MVSD', 'POLYFUSE', 'LDMOS_XTOR', 'FHRES', 'Schottky_diode',
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(1, 222), (5, 222), (12, 222), (14, 222), (15, 222), (21, 10), (63, 63), (204, 10),
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]
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# fmt: on
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def analog_pin_rects(tech: str, uses_vapwr: bool):
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if tech == "sky130A":
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pin_layer = (71, 20) # met4
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via_layers = [(70, 44)] # via3
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for pin_number in range(8):
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if uses_vapwr:
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x1, y1 = 136.17 - 19.32 * pin_number, 0.0
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else:
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x1, y1 = 151.81 - 19.32 * pin_number, 0.0
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x2, y2 = x1 + 0.9, y1 + 1.0
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rect = ((x1, y1), (x2, y2))
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yield (rect, pin_layer, via_layers)
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elif tech == "ihp-sg13g2":
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pin_layer = (126, 0) # TopMetal1
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via_layers = [(125, 0)] # TopVia1
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for pin_number in range(8):
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if uses_vapwr:
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raise NotImplementedError
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else:
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x1, y1 = 190.165 - 24.48 * pin_number, 0.0
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x2, y2 = x1 + 1.75, y1 + 2.0
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rect = ((x1, y1), (x2, y2))
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yield (rect, pin_layer, via_layers)
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elif tech == "gf180mcuD":
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pin_layer = (46, 0) # Metal4
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via_layers = [(40, 0)] # Via3
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for pin_number in range(8):
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if uses_vapwr:
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x1, y1 = 307.90 - 43.68 * pin_number, 0.0
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else:
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x1, y1 = 325.82 - 43.68 * pin_number, 0.0
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x2, y2 = x1 + 3.0, y1 + 1.0
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rect = ((x1, y1), (x2, y2))
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yield (rect, pin_layer, via_layers)
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elif tech in tech_names:
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raise NotImplementedError
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else:
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raise ValueError(f"unexpected tech {tech}")
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valid_layers = {
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"sky130A": valid_layers_sky130A,
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"ihp-sg13g2": valid_layers_ihp_sg13g2,
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"gf180mcuD": valid_layers_gf180mcuD,
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}
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lyp_filename = {
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"sky130A": "sky130A.lyp",
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"ihp-sg13g2": "sg13g2.lyp",
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"gf180mcuD": "gf180mcu.lyp",
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}
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# TODO: read layer numbers from lyp file
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valid_lef_port_layers = {
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"sky130A": {
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"met1.pin": (68, 16),
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"met2.pin": (69, 16),
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"met3.pin": (70, 16),
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"met4.pin": (71, 16),
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},
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"ihp-sg13g2": {
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"Metal1.pin": (8, 2),
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"Metal2.pin": (10, 2),
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"Metal3.pin": (30, 2),
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"Metal4.pin": (50, 2),
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"Metal5.pin": (67, 2),
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"TopMetal1.pin": (126, 2),
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},
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}
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forbidden_layers = {
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"sky130A": [
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"met5.drawing",
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"met5.pin",
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"met5.label",
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],
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"ihp-sg13g2": [
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"TopMetal2.drawing",
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"TopMetal2.pin",
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"TopMetal2.label",
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],
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"gf180mcuD": [
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"Metal5",
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"Metal5_Label",
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],
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}
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power_pins_layer = {
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"sky130A": "met4",
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"ihp-sg13g2": "TopMetal1",
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"gf180mcuD": "Metal4",
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}
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power_pins_min_width = {
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"sky130A": 1200, # 1.2 um
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"ihp-sg13g2": 2100, # 2.1 um
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"gf180mcuD": 1200, # 1.2 um
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}
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boundary_layer = {
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"sky130A": "prBoundary.boundary",
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"ihp-sg13g2": "prBoundary.boundary",
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"gf180mcuD": "PR_bndry",
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}
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