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https://github.com/TinyTapeout/tt-support-tools.git
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htfab
2241597d6b
- no shapes outside project area - VPWR/VGND present, VAPWR present iff uses_3v3 - no invalid layers - cell names don't have '#' or '/' - urpm to nwell spacing satisfies DRC - analog pins have adjacent metal iff marked as used
11 lines
177 B
Plaintext
11 lines
177 B
Plaintext
drc_beol.xml
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drc_feol.xml
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drc_offgrid.xml
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drc_pin_label_purposes_overlapping_drawing.xml
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drc_zero_area.xml
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drc_nwell_urpm.xml
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magic_drc.mag
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magic_drc.txt
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results.md
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results.xml
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