TinyTapeout/tt-support-tools
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tt-support-tools/tech/ihp-sg13g2/def/tt_block_6x2_pgvdd.def
T
Uri Shaked 28fd25f684 refactor: separate tech specific code 
Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
2025-09-13 20:28:48 +03:00

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VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1289280 313740 ) ;
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ROW ROW_1 CoreSite 2880 7560 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 2674 BY 1 STEP 480 0 ;
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ROW ROW_79 CoreSite 2880 302400 FS DO 2674 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 2674 BY 1 STEP 480 0 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 3069 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 3069 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 565 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
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