mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
144 lines
5.0 KiB
Typst
144 lines
5.0 KiB
Typst
#let caravel = {
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align(center,
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table(
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columns: 4,
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align: left,
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table.header(
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[mprj_io_pin], [Function], [Signal], [QFN64 pin]
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),
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`0`, [Input], [`ui_in[0]`], [`31`],
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`1`, [Input], [`ui_in[1]`], [`32`],
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`2`, [Input], [`ui_in[2]`], [`33`],
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`3`, [Input], [`ui_in[3]`], [`34`],
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`4`, [Input], [`ui_in[4]`], [`35`],
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`5`, [Input], [`ui_in[5]`], [`36`],
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`6`, [Input], [`ui_in[6]`], [`37`],
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`7`, [Analog], [`analog[0]`], [`41`],
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`8`, [Analog], [`analog[1]`], [`42`],
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`9`, [Analog], [`analog[2]`], [`43`],
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`10`, [Analog], [`analog[3]`], [`44`],
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`11`, [Analog], [`analog[4]`], [`45`],
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`12`, [Analog], [`analog[5]`], [`46`],
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`13`, [Input], [`ui_in[7]`], [48],
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`14`, [Input], [`clk` $dagger$], [50],
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`15`, [Input], [`rst_n` $dagger$], [`51`],
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`16`, [Bidirectional], [`uio[0]`], [`53`],
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`17`, [Bidirectional], [`uio[1]`], [`54`],
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`18`, [Bidirectional], [`uio[2]`], [`55`],
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`19`, [Bidirectional], [`uio[3]`], [`57`],
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`20`, [Bidirectional], [`uio[4]`], [`58`],
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`21`, [Bidirectional], [`uio[5]`], [`59`],
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`22`, [Bidirectional], [`uio[6]`], [`60`],
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`23`, [Bidirectional], [`uio[7]`], [`61`],
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`24`, [Output], [`uo_out[0]`], [`62`],
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`25`, [Output], [`uo_out[1]`], [`2`],
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`26`, [Output], [`uo_out[2]`], [`3`],
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`27`, [Output], [`uo_out[3]`], [`4`],
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`28`, [Output], [`uo_out[4]`], [`5`],
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`29`, [Output], [`uo_out[5]`], [`6`],
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`30`, [Output], [`uo_out[6]`], [`7`],
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`31`, [Output], [`uo_out[7]`], [`8`],
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`32`, [Analog], [`analog[6]`], [`11`],
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`33`, [Analog], [`analog[7]`], [`12`],
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`34`, [Analog], [`analog[8]`], [`13`],
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`35`, [Analog], [`analog[9]`], [`14`],
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`36`, [Analog], [`analog[10]`], [`15`],
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`37`, [Analog], [`analog[11]`], [`16`],
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`38`, [Mux Control], [`ctrl_ena`], [`22`],
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`39`, [Mux Control], [`ctrl_sel_inc`], [`24`],
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`40`, [Mux Control], [`ctrl_sel_rst_n`], [`25`],
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`41`, [Reserved], [(none)], [`26`],
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`42`, [Reserved], [(none)], [`27`],
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`43`, [Reserved], [(none)], [`28`],
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)
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)
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[
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$dagger$ Internally, there's no difference between `clk`, `rst_n` and `ui_in` pins. They are all just bits in the
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`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
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]
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}
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#let openframe = {
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align(center,
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table(
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columns: 3,
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align: left,
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table.header(
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[QFN64 Pin], [Function], [Signal]
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),
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`1`, [Mux Control], [`ctrl_ena`],
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`2`, [Mux Control], [`ctrl_sel_inc`],
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`3`, [Mux Control], [`ctrl_sel_rst_n`],
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`4`, [Reserved], [(none)],
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`5`, [Reserved], [(none)],
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`6`, [Reserved], [(none)],
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`7`, [Reserved], [(none)],
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`8`, [Reserved], [(none)],
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`9`, [Output], [`uo_out[0]`],
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`10`, [Output], [`uo_out[1]`],
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`11`, [Output], [`uo_out[2]`],
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`12`, [Output], [`uo_out[3]`],
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`13`, [Output], [`uo_out[4]`],
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`14`, [Output], [`uo_out[5]`],
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`15`, [Output], [`uo_out[6]`],
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`16`, [Output], [`uo_out[7]`],
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`17`, [Power], [VDD IO],
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`18`, [Ground], [GND IO],
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`19`, [Analog], [`analog[0]`],
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`20`, [Analog], [`analog[1]`],
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`21`, [Analog], [`analog[2]`],
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`22`, [Analog], [`analog[3]`],
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`23`, [Power], [VAA Analog],
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`24`, [Ground], [GND Analog],
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`25`, [Analog], [`analog[4]`],
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`26`, [Analog], [`analog[5]`],
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`27`, [Analog], [`analog[6]`],
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`28`, [Analog], [`analog[7]`],
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`29`, [Ground], [VDD Core],
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`30`, [Power], [VDD Core],
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`31`, [Ground], [GND IO],
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`32`, [Power], [VDD IO],
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`33`, [Bidirectional], [`uio[0]`],
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`34`, [Bidirectional], [`uio[1]`],
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`35`, [Bidirectional], [`uio[2]`],
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`36`, [Bidirectional], [`uio[3]`],
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`37`, [Bidirectional], [`uio[4]`],
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`38`, [Bidirectional], [`uio[5]`],
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`39`, [Bidirectional], [`uio[6]`],
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`40`, [Bidirectional], [`uio[7]`],
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`41`, [Input], [`ui_in[0]`],
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`42`, [Input], [`ui_in[1]`],
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`43`, [Input], [`ui_in[2]`],
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`44`, [Input], [`ui_in[3]`],
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`45`, [Input], [`ui_in[4]`],
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`46`, [Input], [`ui_in[5]`],
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`47`, [Input], [`ui_in[6]`],
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`48`, [Input], [`ui_in[7]`],
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`49`, [Input], [`rst_n` $dagger$],
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`50`, [Input], [`clk` $dagger$],
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`51`, [Ground], [GND IO],
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`52`, [Power], [VDD IO],
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`53`, [Analog], [`analog[8]`],
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`54`, [Analog], [`analog[9]`],
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`55`, [Analog], [`analog[10]`],
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`56`, [Analog], [`analog[11]`],
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`57`, [Ground], [GND Analog],
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`58`, [Power], [VDD Analog],
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`59`, [Analog], [`analog[12]`],
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`60`, [Analog], [`analog[13]`],
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`61`, [Analog], [`analog[14]`],
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`62`, [Analog], [`analog[15]`],
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`63`, [Ground], [GND Core],
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`64`, [Power], [VDD Core]
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)
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)
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[
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$dagger$ Internally, there's no difference between `clk`, `rst_n` and `ui_in` pins. They are all just bits in the
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`pad_ui_in` bus. However, we use different names to make it easier to understand the purpose of each signal.
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]
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} |