tt-support-tools

mirror of https://github.com/TinyTapeout/tt-support-tools.git synced 2026-11-03 04:36:09 +01:00

Files

T

htfab 2241597d6b feat(precheck): add extra prechecks

- no shapes outside project area
- VPWR/VGND present, VAPWR present iff uses_3v3
- no invalid layers
- cell names don't have '#' or '/'
- urpm to nwell spacing satisfies DRC
- analog pins have adjacent metal iff marked as used

2025-01-31 17:53:57 +02:00

nwell_urpm.drc

feat(precheck): add extra prechecks

2025-01-31 17:53:57 +02:00

pin_label_purposes_overlapping_drawing.rb.drc

feat(precheck): pin_label_purposes_overlapping_drawing check

2024-03-31 21:20:37 +03:00

README.txt

feat(precheck): add extra prechecks

2025-01-31 17:53:57 +02:00

sky130A_mr.drc

chore(precheck): update klayout DRC deck

2024-09-11 23:39:59 +03:00

update.sh

chore(precheck): update klayout DRC deck

2024-09-11 23:39:59 +03:00

zeroarea.rb.drc

feat(precheck): add zeroarea check

2024-04-20 00:36:09 +03:00

README.txt

sky130A_mr.drc from https://github.com/efabless/mpw_precheck revision 3467a4c8252aa884cddc7d3f73370df9744dd65e
pin_label_purposes_overlapping_drawing.rb.drc from https://github.com/efabless/mpw_precheck revision f6b9c3d3f00694f96dce8444149449b4719180f0
zeroarea.rb.drc from https://github.com/efabless/mpw_precheck revision 4fd5283b124e931c9e71219f47270075176f84e2
nwell_urpm.drc from https://open-source-silicon.slack.com/archives/C05FW1VMY5A/p1729112262642699?thread_ts=1728921677.220509&cid=C05FW1VMY5A