mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
58 lines
1.5 KiB
Python
58 lines
1.5 KiB
Python
import git
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segment_font = {
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" ": 0b00000000,
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"0": 0b00111111,
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"1": 0b00000110,
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"2": 0b01011011,
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"3": 0b01001111,
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"4": 0b01100110,
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"5": 0b01101101,
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"6": 0b01111101,
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"7": 0b00000111,
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"8": 0b01111111,
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"9": 0b01101111,
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"A": 0b01110111,
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"B": 0b01111100,
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"C": 0b00111001,
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"D": 0b01011110,
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"E": 0b01111001,
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"F": 0b01110001,
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"t": 0b01111000,
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}
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def segment_char(c):
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return segment_font[c]
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class ROMFile:
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def __init__(self, config, projects):
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self.projects = projects
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self.config = config
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def get_git_remote(self):
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return list(git.Repo(".").remotes[0].urls)[0]
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def get_git_commit_hash(self):
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return git.Repo(".").commit().hexsha
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def write_rom(self):
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rom = bytearray(256)
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short_sha = self.get_git_commit_hash()[:8]
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rom_text = f"shuttle={self.config['name']}\n"
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rom_text += f"repo={self.get_git_remote()}\n"
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rom_text += f"commit={short_sha}\n"
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assert len(rom_text) < 96, "ROM text too long"
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rom[0:4] = map(segment_char, "tt04")
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rom[8:16] = map(segment_char, short_sha.upper())
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rom[32 : 32 + len(rom_text)] = rom_text.encode("ascii")
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# build complete list of filenames for sim
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with open("verilog/includes/rom_tile.vmem", "w") as fh:
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for line in range(0, len(rom), 16):
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for byte in range(0, 16):
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fh.write("{:02x} ".format(rom[line + byte]))
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fh.write("\n")
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