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56 lines
1.8 KiB
Tcl
56 lines
1.8 KiB
Tcl
# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2024-2026 Tiny Tapeout LTD
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# Author: Uri Shaked
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# Description: This script initializes a new Magic project for an analog design on Tiny Tapeout.
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# Important: before running this script, download the the .def file from
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# https://raw.githubusercontent.com/TinyTapeout/tt-support-tools/main/tech/ihp-sg13cmos5l/def/analog/tt_analog_1x2.def
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#
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# SG13CMOS5L requires Magic 8.3.657 or newer.
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# Change the settings below to match your design:
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# ------------------------------------------------
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set TOP_LEVEL_CELL tt_um_analog_example
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set TEMPLATE_FILE tt_analog_1x2.def
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set POWER_STRIPE_WIDTH 2.4um ;# The minimum width is 2.1um
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# Power stripes: NET name, x position. You can add additional power stripes for each net, as needed.
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# Keep the stripes at least 1um apart. Power stripes go on Metal4: TopMetal1 is reserved for the chip-level power grid.
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set POWER_STRIPES {
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VDPWR 1um
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VGND 6um
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}
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# Read in the pin positions
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# -------------------------
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def read $TEMPLATE_FILE
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cellname rename tt_um_template $TOP_LEVEL_CELL
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# Draw the power stripes
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# --------------------------------
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proc draw_power_stripe {name x} {
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global POWER_STRIPE_WIDTH
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box $x 5um $x 308um
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box width $POWER_STRIPE_WIDTH
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paint met4
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label $name FreeSans 0.25u -met4
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port make
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port use [expr {$name eq "VGND" ? "ground" : "power"}]
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port class bidirectional
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port connections n s e w
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}
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# You can extra power stripes, as you need.
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foreach {name x} $POWER_STRIPES {
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puts "Drawing power stripe $name at $x"
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draw_power_stripe $name $x
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}
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# Save the layout and export GDS/LEF
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# ----------------------------------
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save ${TOP_LEVEL_CELL}.mag
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file mkdir gds
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gds write gds/${TOP_LEVEL_CELL}.gds
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file mkdir lef
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lef write lef/${TOP_LEVEL_CELL}.lef -hide -pinonly
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