TinyTapeout/tt-support-tools
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tt-support-tools/ihp/def/tt_block_4x1_pgvdd.def
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VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 854400 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1768 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1768 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1768 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 2034 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 2034 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1779 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 374 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 213 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 37440 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33600 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 29760 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
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