TinyTapeout/tt-support-tools
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tt-support-tools/tech/ihp-sg13g2/def/tt_block_6x4_pgvdd.def
T
Uri Shaked c35546a7e4 feat(tech/ihp-sg13g2): update user project .def files 
This change moves the power rails to TopMetal1, and makes the TopMetal1 layer available for the user designs.

In addition, we now let LibreLane install the PDK instead of having to install it separately.
2025-11-23 19:13:21 +02:00

433 lines
21 KiB
Modula-2
Raw Blame History

VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1289280 710640 ) ;
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TRACKS X 480 DO 2685 STEP 480 LAYER Metal1 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal2 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal4 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2685 STEP 480 LAYER Metal5 ;
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal5 ;
TRACKS X 1640 DO 565 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 177 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 710140 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 710140 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 710140 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 710140 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 710140 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 710140 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 710140 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 710140 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 710140 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 710140 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 710140 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 710140 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 710140 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 710140 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 710140 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 710140 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 710140 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 710140 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 710140 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 710140 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 710140 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 710140 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 710140 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 710140 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 37440 710140 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33600 710140 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 29760 710140 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 710140 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 710140 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 710140 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 710140 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 710140 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 710140 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 710140 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 710140 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 710140 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 710140 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 710140 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 710140 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 710140 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 710140 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 710140 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 710140 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
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