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Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
5 lines
59 B
Verilog
5 lines
59 B
Verilog
`default_nettype none
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module tt_logo_corner ();
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endmodule
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