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fix: hardening wokwi modules fail
rename `user_module_<wokwi_id>` to `tt_um_<wokwi_id>`
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@@ -9,7 +9,7 @@ TOPLEVEL_LANG ?= verilog
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ifneq ($(GATES),yes)
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# this is the only part you should need to modify:
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VERILOG_SOURCES += $(PWD)/cells.v $(PWD)/user_module_WOKWI_ID.v $(PWD)/test_wokwi.v
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VERILOG_SOURCES += $(PWD)/cells.v $(PWD)/tt_um_wokwi_WOKWI_ID.v $(PWD)/test_wokwi.v
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else
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@@ -6,7 +6,7 @@ module test_wokwi ();
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wire [7:0] io_out;
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wire [7:0] io_in;
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user_module_WOKWI_ID dut (
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tt_um_wokwi_WOKWI_ID dut (
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`ifdef GL_TEST
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.vccd1( 1'b1),
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.vssd1( 1'b0),
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