mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
feat: add ihp-sg13cmos5l PDK alongside ihp-sg13g2
Based on work done in the ihp-sg13cmos5l branch
This commit is contained in:
Uri Shaked
@@ -0,0 +1,70 @@
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{
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"categories" : [
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"AND",
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"OR",
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"NAND",
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"NOR",
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"Clock",
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"Flip Flops",
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||||
"Multiplexer",
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||||
"Latch",
|
||||
"Inverter",
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||||
"Buffer",
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||||
"Fill",
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||||
"Tap",
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||||
"Diode",
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"Combo Logic",
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||||
"Misc"
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],
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"map" : {
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||||
"a21o" : 13,
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"a21oi" : 13,
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"a22oi" : 13,
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||||
"a221oi" : 13,
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||||
"and2" : 0,
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||||
"and3" : 0,
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||||
"and4" : 0,
|
||||
"antennanp" : 12,
|
||||
"buf" : 9,
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||||
"decap" : 10,
|
||||
"dfrbp" : 5,
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||||
"dfrbpq": 5,
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"dlhq" : 7,
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||||
"dlhr" : 7,
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||||
"dlhrq" : 7,
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||||
"dllr" : 7,
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||||
"dllrq" : 7,
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||||
"dlygate4sd1" : 14,
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"dlygate4sd2" : 14,
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"dlygate4sd3" : 14,
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"ebufn" : 14,
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"einvn" : 14,
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"fill" : 10,
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"inv" : 8,
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"lgcp" : 4,
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"mux2" : 6,
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"mux4" : 6,
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"nand2" : 2,
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"nand2b" : 2,
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"nand3" : 2,
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"nand3b" : 2,
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"nand4" : 2,
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"nor2" : 3,
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"nor2b" : 3,
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"nor3" : 3,
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"nor4" : 3,
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"o21ai" : 13,
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"or2" : 1,
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"or3" : 1,
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"or4" : 1,
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"sdfbbp" : 5,
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"sdfrbp" : 5,
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"sdfrbpq" : 5,
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"sighold" : 14,
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"slgcp" : 4,
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"tiehi" : 14,
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"tielo" : 14,
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"xnor2" : 3,
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"xor2" : 1
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}
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}
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@@ -0,0 +1,247 @@
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{
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"a21o" : {
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"description" : "2-input AND into first input of 2-input OR.",
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"doc_name": "AO21x",
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"doc_ref" : 7
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},
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"a21oi" : {
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"description" : "2-input AND into first input of 2-input NOR.",
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"doc_name": "A21OIx",
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"doc_ref" : 1
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},
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"a221oi" : {
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"description" : "2-input AND into first two inputs of 3-input NOR.",
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"doc_name": "A221OI",
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"doc_ref" : 2
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},
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"a22oi" : {
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"description" : "2-input AND into both inputs of 2-input NOR.",
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"doc_name": "A22OI",
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"doc_ref" : 3
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},
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"and2" : {
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"description" : "2-input AND.",
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"doc_name": "AND2x",
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"doc_ref" : 4
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},
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"and3" : {
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"description" : "3-input AND.",
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"doc_name": "AND3x",
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"doc_ref" : 5
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},
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"and4" : {
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"description" : "4-input AND.",
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"doc_name": "AND4x",
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"doc_ref" : 6
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},
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"antennanp" : {
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"description" : "Antenna tie-down diode.",
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"doc_name": "NP_ANT",
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"doc_ref" : 38
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},
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"buf" : {
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"description" : "Buffer.",
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"doc_name": "BUx",
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"doc_ref" : 9
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},
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"decap" : {
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"description" : "Decoupling capacitance filler.",
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"doc_name": "DECAPx",
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"doc_ref" : 10
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},
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"dfrbp" : {
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"description" : "Delay flop, inverted reset, complementary outputs.",
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"doc_name": "DFFRRx",
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"doc_ref" : 11
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},
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"dfrbpq": {
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"description" : "Delay flop, inverted reset, single output.",
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"doc_name": "DFRBPQx",
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||||
"doc_ref" : 0
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||||
},
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||||
"dlhq" : {
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"description" : "Delay latch, non-inverted enable, single output.",
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"doc_name": "DLHQ",
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||||
"doc_ref" : 12
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},
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||||
"dlhr" : {
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"description" : "Delay latch, inverted reset, non-inverted enable, complementary outputs.",
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"doc_name": "DLHR",
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"doc_ref" : 14
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||||
},
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||||
"dlhrq" : {
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"description" : "Delay latch, inverted reset, non-inverted enable, single output.",
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"doc_name": "DLHRQ",
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"doc_ref" : 13
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||||
},
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||||
"dllr" : {
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||||
"description" : "Delay latch, inverted reset, inverted enable, complementary outputs.",
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||||
"doc_name": "DLLR",
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||||
"doc_ref" : 16
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||||
},
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||||
"dllrq" : {
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||||
"description" : "Delay latch, inverted reset, inverted enable, single output.",
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||||
"doc_name": "DLLRQ",
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||||
"doc_ref" : 15
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},
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||||
"dlygate4sd1" : {
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"description" : "Delay Buffer 4-stage ... length inner stage gates.",
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"doc_name": "DLY1",
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"doc_ref" : 17
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},
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"dlygate4sd2" : {
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"description" : "Delay Buffer 4-stage ... length inner stage gates.",
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"doc_name": "DLY2",
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||||
"doc_ref" : 18
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},
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||||
"dlygate4sd3" : {
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"description" : "Delay Buffer 4-stage ... length inner stage gates.",
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"doc_name": "DLY4",
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||||
"doc_ref" : 19
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||||
},
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||||
"ebufn" : {
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||||
"description" : "Tri-state buffer, negative enable.",
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||||
"doc_name": "BTLx",
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||||
"doc_ref" : 8
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||||
},
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||||
"einvn" : {
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||||
"description" : "Tri-state inverter, negative enable.",
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||||
"doc_name": "EINVINx, ITL",
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||||
"doc_ref" : 20
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||||
},
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||||
"fill" : {
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||||
"description" : "Fill cell.",
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||||
"doc_name": "FILLx",
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||||
"doc_ref" : 21
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},
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||||
"inv" : {
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"description" : "Inverter.",
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"doc_name": "INx",
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"doc_ref" : 23
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},
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||||
"lgcp" : {
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||||
"description" : "Clock gate.",
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"doc_name": "GCLK",
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||||
"doc_ref" : 22
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},
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||||
"mux2" : {
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||||
"description" : "2-input multiplexer.",
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"doc_name": "MUX2x",
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||||
"doc_ref" : 26
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},
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"mux4" : {
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"description" : "4-input multiplexer.",
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"doc_name": "MUX4",
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"doc_ref" : 27
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},
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"nand2" : {
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"description" : "2-input NAND.",
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"doc_name": "NAND2x",
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"doc_ref" : 30
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},
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"nand2b" : {
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"description" : "2-input NAND, first input inverted.",
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"doc_name": "NAND2B1, NAND2B2",
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"doc_ref" : 28
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},
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||||
"nand3" : {
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"description" : "3-input NAND.",
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"doc_name": "NAND3",
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"doc_ref" : 32
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},
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"nand3b" : {
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"description" : "3-input NAND, first input inverted.",
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"doc_name": "NAND3B1",
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"doc_ref" : 31
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},
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||||
"nand4" : {
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"description" : "4-input NAND.",
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||||
"doc_name": "NAND4",
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||||
"doc_ref" : 33
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},
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||||
"nor2" : {
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"description" : "2-input NOR.",
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"doc_name": "NOR2x",
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"doc_ref" : 35
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},
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"nor2b" : {
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"description" : "2-input NOR, first input inverted.",
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"doc_name": "NOR2Bx",
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||||
"doc_ref" : 34
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},
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||||
"nor3" : {
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"description" : "3-input NOR.",
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||||
"doc_name": "NOR3x",
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||||
"doc_ref" : 36
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},
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||||
"nor4" : {
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"description" : "4-input NOR.",
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"doc_name": "NOR4x",
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"doc_ref" : 37
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},
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||||
"o21ai" : {
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"description" : "2-input OR into first input of 2-input NAND.",
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"doc_name": "O21AI",
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"doc_ref" : 39
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},
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"or2" : {
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"description" : "2-input OR.",
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"doc_name": "OR2x",
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"doc_ref" : 40
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},
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||||
"or3" : {
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"description" : "3-input OR.",
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"doc_name": "OR3x",
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"doc_ref" : 41
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},
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"or4" : {
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"description" : "4-input OR.",
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"doc_name": "OR4x",
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"doc_ref" : 42
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},
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||||
"sdfbbp" : {
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"description" : "Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.",
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"doc_name": "SDFRRS",
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"doc_ref" : 43
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},
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"sdfrbp": {
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"description" : "Scan delay flop, inverted reset, non-inverted clock, complementary outputs.",
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"doc_name": "SDFRBPx",
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"doc_ref" : 0
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},
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||||
"sdfrbpq": {
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"description" : "Scan delay flop, inverted reset, non-inverted clock, single output.",
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"doc_name": "SDFRBPQx",
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"doc_ref" : 0
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},
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||||
"sighold" : {
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"description" : "Cross-coupled inverters.",
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"doc_name": "KEEPSTATE",
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||||
"doc_ref" : 25
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},
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||||
"slgcp" : {
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"description" : "Scan gated clock.",
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"doc_name": "SGCLK",
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"doc_ref" : 44
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},
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"tiehi" : {
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"description" : "Constant high output.",
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"doc_name": "TIE1",
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"doc_ref" : 46
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},
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"tielo" : {
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"description" : "Constant low output.",
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||||
"doc_name": "TIE0",
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||||
"doc_ref" : 45
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||||
},
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||||
"xnor2" : {
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||||
"description" : "2-input exclusive NOR.",
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||||
"doc_name": "XNOR2_1",
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||||
"doc_ref" : 47
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||||
},
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||||
"xor2" : {
|
||||
"description" : "2-input exclusive OR.",
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||||
"doc_name": "XOR2_1",
|
||||
"doc_ref" : 48
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||||
}
|
||||
}
|
||||
@@ -0,0 +1,281 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 202080 154980 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 409 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 420 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 368 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 420 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 368 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 420 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 88 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 67 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 154480 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 154480 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 154480 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 154480 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 154480 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 154480 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 154480 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 154480 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 154480 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 154480 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 154480 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 154480 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 154480 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 154480 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 154480 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 154480 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 154480 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 154480 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 154480 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 154480 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 154480 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 154480 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 154480 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 154480 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 154480 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 154480 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 154480 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 154480 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 154480 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 154480 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 154480 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 154480 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 154480 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 154480 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 154480 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 154480 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 154480 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 154480 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 154480 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 154480 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 154480 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 154480 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 154480 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,323 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 202080 313740 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 409 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 409 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 420 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 420 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 420 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 420 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 88 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 313240 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 313240 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 313240 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 313240 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 313240 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 313240 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 313240 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 313240 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 313240 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 313240 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 313240 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 313240 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 313240 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 313240 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 313240 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 313240 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 313240 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 313240 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 313240 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 313240 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 313240 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 313240 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 313240 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 313240 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 313240 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 313240 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 313240 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 313240 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 313240 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 313240 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 313240 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 313240 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 313240 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 313240 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 313240 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 313240 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 313240 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 313240 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 313240 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 313240 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 313240 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 313240 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 313240 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,323 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 419520 313740 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 862 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 862 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 873 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 873 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 873 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 873 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 183 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 313240 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 313240 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 313240 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 313240 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 313240 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 313240 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 313240 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 313240 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 313240 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 313240 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 313240 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 313240 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 313240 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 313240 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 313240 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 313240 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 313240 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 313240 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 313240 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 313240 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 313240 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 313240 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 313240 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 313240 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 313240 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 313240 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 313240 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 313240 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 313240 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 313240 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 313240 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 313240 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 313240 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 313240 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 313240 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 313240 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 313240 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 313240 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 313240 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 313240 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 313240 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 313240 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 313240 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,323 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 636960 313740 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 1315 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 1326 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 1326 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 1326 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 1326 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 279 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 313240 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 313240 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 313240 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 313240 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 313240 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 313240 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 313240 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 313240 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 313240 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 313240 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 313240 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 313240 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 313240 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 313240 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 313240 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 313240 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 313240 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 313240 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 313240 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 313240 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 313240 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 313240 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 313240 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 313240 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 313240 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 313240 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 313240 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 313240 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 313240 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 313240 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 313240 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 313240 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 313240 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 313240 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 313240 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 313240 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 313240 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 313240 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 313240 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 313240 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 313240 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 313240 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 313240 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,428 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 636960 710640 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_81 CoreSite 2880 309960 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_82 CoreSite 2880 313740 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_83 CoreSite 2880 317520 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_84 CoreSite 2880 321300 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_85 CoreSite 2880 325080 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_86 CoreSite 2880 328860 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_87 CoreSite 2880 332640 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_88 CoreSite 2880 336420 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_89 CoreSite 2880 340200 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_90 CoreSite 2880 343980 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_91 CoreSite 2880 347760 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_92 CoreSite 2880 351540 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_93 CoreSite 2880 355320 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_94 CoreSite 2880 359100 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_95 CoreSite 2880 362880 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_96 CoreSite 2880 366660 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_97 CoreSite 2880 370440 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_98 CoreSite 2880 374220 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_99 CoreSite 2880 378000 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_100 CoreSite 2880 381780 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_101 CoreSite 2880 385560 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_102 CoreSite 2880 389340 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_103 CoreSite 2880 393120 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_104 CoreSite 2880 396900 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_105 CoreSite 2880 400680 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_106 CoreSite 2880 404460 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_107 CoreSite 2880 408240 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_108 CoreSite 2880 412020 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_109 CoreSite 2880 415800 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_110 CoreSite 2880 419580 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_111 CoreSite 2880 423360 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_112 CoreSite 2880 427140 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_113 CoreSite 2880 430920 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_114 CoreSite 2880 434700 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_115 CoreSite 2880 438480 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_116 CoreSite 2880 442260 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_117 CoreSite 2880 446040 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_118 CoreSite 2880 449820 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_119 CoreSite 2880 453600 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_120 CoreSite 2880 457380 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_121 CoreSite 2880 461160 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_122 CoreSite 2880 464940 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_123 CoreSite 2880 468720 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_124 CoreSite 2880 472500 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_125 CoreSite 2880 476280 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_126 CoreSite 2880 480060 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_127 CoreSite 2880 483840 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_128 CoreSite 2880 487620 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_129 CoreSite 2880 491400 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_130 CoreSite 2880 495180 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_131 CoreSite 2880 498960 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_132 CoreSite 2880 502740 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_133 CoreSite 2880 506520 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_134 CoreSite 2880 510300 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_135 CoreSite 2880 514080 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_136 CoreSite 2880 517860 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_137 CoreSite 2880 521640 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_138 CoreSite 2880 525420 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_139 CoreSite 2880 529200 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_140 CoreSite 2880 532980 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_141 CoreSite 2880 536760 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_142 CoreSite 2880 540540 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_143 CoreSite 2880 544320 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_144 CoreSite 2880 548100 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_145 CoreSite 2880 551880 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_146 CoreSite 2880 555660 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_147 CoreSite 2880 559440 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_148 CoreSite 2880 563220 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_149 CoreSite 2880 567000 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_150 CoreSite 2880 570780 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_151 CoreSite 2880 574560 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_152 CoreSite 2880 578340 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_153 CoreSite 2880 582120 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_154 CoreSite 2880 585900 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_155 CoreSite 2880 589680 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_156 CoreSite 2880 593460 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_157 CoreSite 2880 597240 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_158 CoreSite 2880 601020 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_159 CoreSite 2880 604800 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_160 CoreSite 2880 608580 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_161 CoreSite 2880 612360 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_162 CoreSite 2880 616140 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_163 CoreSite 2880 619920 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_164 CoreSite 2880 623700 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_165 CoreSite 2880 627480 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_166 CoreSite 2880 631260 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_167 CoreSite 2880 635040 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_168 CoreSite 2880 638820 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_169 CoreSite 2880 642600 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_170 CoreSite 2880 646380 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_171 CoreSite 2880 650160 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_172 CoreSite 2880 653940 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_173 CoreSite 2880 657720 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_174 CoreSite 2880 661500 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_175 CoreSite 2880 665280 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_176 CoreSite 2880 669060 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_177 CoreSite 2880 672840 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_178 CoreSite 2880 676620 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_179 CoreSite 2880 680400 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_180 CoreSite 2880 684180 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_181 CoreSite 2880 687960 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_182 CoreSite 2880 691740 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_183 CoreSite 2880 695520 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_184 CoreSite 2880 699300 N DO 1315 BY 1 STEP 480 0 ;
|
||||
ROW ROW_185 CoreSite 2880 703080 FS DO 1315 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 1326 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 1326 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 1326 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 1326 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 279 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 710140 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 710140 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 710140 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 710140 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 710140 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 710140 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 710140 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 710140 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 710140 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 710140 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 710140 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 710140 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 710140 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 710140 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 710140 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 710140 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 710140 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 710140 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 710140 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 710140 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 710140 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 710140 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 710140 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 710140 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 710140 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 710140 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 710140 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 710140 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 710140 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 710140 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 710140 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 710140 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 710140 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 710140 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 710140 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 710140 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 710140 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 710140 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 710140 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 710140 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 710140 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 710140 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 710140 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,323 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 854400 313740 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 1768 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 1779 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 1779 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 1779 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 374 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 313240 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 313240 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 313240 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 313240 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 313240 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 313240 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 313240 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 313240 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 313240 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 313240 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 313240 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 313240 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 313240 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 313240 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 313240 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 313240 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 313240 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 313240 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 313240 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 313240 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 313240 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 313240 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 313240 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 313240 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 313240 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 313240 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 313240 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 313240 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 313240 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 313240 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 313240 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 313240 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 313240 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 313240 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 313240 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 313240 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 313240 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 313240 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 313240 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 313240 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 313240 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 313240 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 313240 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,428 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 854400 710640 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_81 CoreSite 2880 309960 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_82 CoreSite 2880 313740 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_83 CoreSite 2880 317520 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_84 CoreSite 2880 321300 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_85 CoreSite 2880 325080 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_86 CoreSite 2880 328860 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_87 CoreSite 2880 332640 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_88 CoreSite 2880 336420 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_89 CoreSite 2880 340200 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_90 CoreSite 2880 343980 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_91 CoreSite 2880 347760 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_92 CoreSite 2880 351540 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_93 CoreSite 2880 355320 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_94 CoreSite 2880 359100 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_95 CoreSite 2880 362880 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_96 CoreSite 2880 366660 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_97 CoreSite 2880 370440 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_98 CoreSite 2880 374220 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_99 CoreSite 2880 378000 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_100 CoreSite 2880 381780 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_101 CoreSite 2880 385560 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_102 CoreSite 2880 389340 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_103 CoreSite 2880 393120 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_104 CoreSite 2880 396900 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_105 CoreSite 2880 400680 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_106 CoreSite 2880 404460 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_107 CoreSite 2880 408240 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_108 CoreSite 2880 412020 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_109 CoreSite 2880 415800 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_110 CoreSite 2880 419580 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_111 CoreSite 2880 423360 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_112 CoreSite 2880 427140 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_113 CoreSite 2880 430920 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_114 CoreSite 2880 434700 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_115 CoreSite 2880 438480 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_116 CoreSite 2880 442260 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_117 CoreSite 2880 446040 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_118 CoreSite 2880 449820 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_119 CoreSite 2880 453600 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_120 CoreSite 2880 457380 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_121 CoreSite 2880 461160 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_122 CoreSite 2880 464940 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_123 CoreSite 2880 468720 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_124 CoreSite 2880 472500 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_125 CoreSite 2880 476280 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_126 CoreSite 2880 480060 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_127 CoreSite 2880 483840 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_128 CoreSite 2880 487620 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_129 CoreSite 2880 491400 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_130 CoreSite 2880 495180 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_131 CoreSite 2880 498960 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_132 CoreSite 2880 502740 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_133 CoreSite 2880 506520 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_134 CoreSite 2880 510300 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_135 CoreSite 2880 514080 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_136 CoreSite 2880 517860 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_137 CoreSite 2880 521640 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_138 CoreSite 2880 525420 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_139 CoreSite 2880 529200 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_140 CoreSite 2880 532980 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_141 CoreSite 2880 536760 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_142 CoreSite 2880 540540 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_143 CoreSite 2880 544320 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_144 CoreSite 2880 548100 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_145 CoreSite 2880 551880 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_146 CoreSite 2880 555660 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_147 CoreSite 2880 559440 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_148 CoreSite 2880 563220 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_149 CoreSite 2880 567000 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_150 CoreSite 2880 570780 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_151 CoreSite 2880 574560 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_152 CoreSite 2880 578340 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_153 CoreSite 2880 582120 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_154 CoreSite 2880 585900 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_155 CoreSite 2880 589680 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_156 CoreSite 2880 593460 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_157 CoreSite 2880 597240 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_158 CoreSite 2880 601020 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_159 CoreSite 2880 604800 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_160 CoreSite 2880 608580 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_161 CoreSite 2880 612360 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_162 CoreSite 2880 616140 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_163 CoreSite 2880 619920 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_164 CoreSite 2880 623700 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_165 CoreSite 2880 627480 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_166 CoreSite 2880 631260 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_167 CoreSite 2880 635040 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_168 CoreSite 2880 638820 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_169 CoreSite 2880 642600 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_170 CoreSite 2880 646380 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_171 CoreSite 2880 650160 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_172 CoreSite 2880 653940 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_173 CoreSite 2880 657720 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_174 CoreSite 2880 661500 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_175 CoreSite 2880 665280 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_176 CoreSite 2880 669060 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_177 CoreSite 2880 672840 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_178 CoreSite 2880 676620 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_179 CoreSite 2880 680400 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_180 CoreSite 2880 684180 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_181 CoreSite 2880 687960 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_182 CoreSite 2880 691740 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_183 CoreSite 2880 695520 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_184 CoreSite 2880 699300 N DO 1768 BY 1 STEP 480 0 ;
|
||||
ROW ROW_185 CoreSite 2880 703080 FS DO 1768 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 1779 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 1779 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 1779 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 1779 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 374 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 710140 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 710140 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 710140 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 710140 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 710140 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 710140 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 710140 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 710140 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 710140 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 710140 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 710140 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 710140 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 710140 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 710140 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 710140 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 710140 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 710140 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 710140 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 710140 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 710140 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 710140 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 710140 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 710140 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 710140 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 710140 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 710140 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 710140 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 710140 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 710140 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 710140 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 710140 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 710140 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 710140 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 710140 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 710140 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 710140 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 710140 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 710140 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 710140 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 710140 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 710140 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 710140 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 710140 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,428 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 1071840 710640 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_81 CoreSite 2880 309960 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_82 CoreSite 2880 313740 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_83 CoreSite 2880 317520 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_84 CoreSite 2880 321300 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_85 CoreSite 2880 325080 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_86 CoreSite 2880 328860 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_87 CoreSite 2880 332640 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_88 CoreSite 2880 336420 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_89 CoreSite 2880 340200 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_90 CoreSite 2880 343980 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_91 CoreSite 2880 347760 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_92 CoreSite 2880 351540 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_93 CoreSite 2880 355320 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_94 CoreSite 2880 359100 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_95 CoreSite 2880 362880 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_96 CoreSite 2880 366660 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_97 CoreSite 2880 370440 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_98 CoreSite 2880 374220 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_99 CoreSite 2880 378000 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_100 CoreSite 2880 381780 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_101 CoreSite 2880 385560 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_102 CoreSite 2880 389340 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_103 CoreSite 2880 393120 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_104 CoreSite 2880 396900 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_105 CoreSite 2880 400680 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_106 CoreSite 2880 404460 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_107 CoreSite 2880 408240 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_108 CoreSite 2880 412020 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_109 CoreSite 2880 415800 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_110 CoreSite 2880 419580 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_111 CoreSite 2880 423360 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_112 CoreSite 2880 427140 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_113 CoreSite 2880 430920 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_114 CoreSite 2880 434700 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_115 CoreSite 2880 438480 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_116 CoreSite 2880 442260 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_117 CoreSite 2880 446040 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_118 CoreSite 2880 449820 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_119 CoreSite 2880 453600 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_120 CoreSite 2880 457380 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_121 CoreSite 2880 461160 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_122 CoreSite 2880 464940 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_123 CoreSite 2880 468720 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_124 CoreSite 2880 472500 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_125 CoreSite 2880 476280 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_126 CoreSite 2880 480060 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_127 CoreSite 2880 483840 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_128 CoreSite 2880 487620 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_129 CoreSite 2880 491400 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_130 CoreSite 2880 495180 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_131 CoreSite 2880 498960 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_132 CoreSite 2880 502740 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_133 CoreSite 2880 506520 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_134 CoreSite 2880 510300 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_135 CoreSite 2880 514080 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_136 CoreSite 2880 517860 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_137 CoreSite 2880 521640 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_138 CoreSite 2880 525420 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_139 CoreSite 2880 529200 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_140 CoreSite 2880 532980 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_141 CoreSite 2880 536760 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_142 CoreSite 2880 540540 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_143 CoreSite 2880 544320 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_144 CoreSite 2880 548100 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_145 CoreSite 2880 551880 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_146 CoreSite 2880 555660 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_147 CoreSite 2880 559440 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_148 CoreSite 2880 563220 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_149 CoreSite 2880 567000 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_150 CoreSite 2880 570780 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_151 CoreSite 2880 574560 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_152 CoreSite 2880 578340 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_153 CoreSite 2880 582120 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_154 CoreSite 2880 585900 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_155 CoreSite 2880 589680 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_156 CoreSite 2880 593460 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_157 CoreSite 2880 597240 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_158 CoreSite 2880 601020 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_159 CoreSite 2880 604800 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_160 CoreSite 2880 608580 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_161 CoreSite 2880 612360 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_162 CoreSite 2880 616140 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_163 CoreSite 2880 619920 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_164 CoreSite 2880 623700 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_165 CoreSite 2880 627480 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_166 CoreSite 2880 631260 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_167 CoreSite 2880 635040 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_168 CoreSite 2880 638820 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_169 CoreSite 2880 642600 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_170 CoreSite 2880 646380 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_171 CoreSite 2880 650160 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_172 CoreSite 2880 653940 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_173 CoreSite 2880 657720 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_174 CoreSite 2880 661500 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_175 CoreSite 2880 665280 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_176 CoreSite 2880 669060 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_177 CoreSite 2880 672840 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_178 CoreSite 2880 676620 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_179 CoreSite 2880 680400 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_180 CoreSite 2880 684180 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_181 CoreSite 2880 687960 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_182 CoreSite 2880 691740 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_183 CoreSite 2880 695520 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_184 CoreSite 2880 699300 N DO 2221 BY 1 STEP 480 0 ;
|
||||
ROW ROW_185 CoreSite 2880 703080 FS DO 2221 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 2232 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 2232 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 2232 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 2232 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 470 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 710140 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 710140 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 710140 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 710140 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 710140 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 710140 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 710140 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 710140 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 710140 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 710140 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 710140 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 710140 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 710140 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 710140 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 710140 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 710140 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 710140 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 710140 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 710140 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 710140 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 710140 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 710140 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 710140 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 710140 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 710140 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 710140 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 710140 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 710140 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 710140 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 710140 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 710140 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 710140 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 710140 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 710140 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 710140 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 710140 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 710140 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 710140 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 710140 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 710140 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 710140 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 710140 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 710140 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,323 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 1289280 313740 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 2674 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 2685 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 2685 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 2685 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 565 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 313240 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 313240 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 313240 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 313240 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 313240 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 313240 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 313240 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 313240 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 313240 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 313240 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 313240 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 313240 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 313240 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 313240 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 313240 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 313240 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 313240 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 313240 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 313240 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 313240 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 313240 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 313240 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 313240 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 313240 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 313240 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 313240 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 313240 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 313240 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 313240 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 313240 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 313240 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 313240 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 313240 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 313240 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 313240 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 313240 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 313240 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 313240 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 313240 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 313240 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 313240 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 313240 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 313240 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,428 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 1289280 710640 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_81 CoreSite 2880 309960 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_82 CoreSite 2880 313740 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_83 CoreSite 2880 317520 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_84 CoreSite 2880 321300 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_85 CoreSite 2880 325080 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_86 CoreSite 2880 328860 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_87 CoreSite 2880 332640 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_88 CoreSite 2880 336420 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_89 CoreSite 2880 340200 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_90 CoreSite 2880 343980 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_91 CoreSite 2880 347760 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_92 CoreSite 2880 351540 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_93 CoreSite 2880 355320 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_94 CoreSite 2880 359100 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_95 CoreSite 2880 362880 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_96 CoreSite 2880 366660 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_97 CoreSite 2880 370440 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_98 CoreSite 2880 374220 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_99 CoreSite 2880 378000 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_100 CoreSite 2880 381780 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_101 CoreSite 2880 385560 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_102 CoreSite 2880 389340 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_103 CoreSite 2880 393120 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_104 CoreSite 2880 396900 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_105 CoreSite 2880 400680 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_106 CoreSite 2880 404460 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_107 CoreSite 2880 408240 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_108 CoreSite 2880 412020 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_109 CoreSite 2880 415800 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_110 CoreSite 2880 419580 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_111 CoreSite 2880 423360 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_112 CoreSite 2880 427140 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_113 CoreSite 2880 430920 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_114 CoreSite 2880 434700 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_115 CoreSite 2880 438480 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_116 CoreSite 2880 442260 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_117 CoreSite 2880 446040 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_118 CoreSite 2880 449820 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_119 CoreSite 2880 453600 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_120 CoreSite 2880 457380 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_121 CoreSite 2880 461160 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_122 CoreSite 2880 464940 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_123 CoreSite 2880 468720 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_124 CoreSite 2880 472500 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_125 CoreSite 2880 476280 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_126 CoreSite 2880 480060 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_127 CoreSite 2880 483840 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_128 CoreSite 2880 487620 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_129 CoreSite 2880 491400 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_130 CoreSite 2880 495180 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_131 CoreSite 2880 498960 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_132 CoreSite 2880 502740 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_133 CoreSite 2880 506520 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_134 CoreSite 2880 510300 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_135 CoreSite 2880 514080 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_136 CoreSite 2880 517860 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_137 CoreSite 2880 521640 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_138 CoreSite 2880 525420 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_139 CoreSite 2880 529200 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_140 CoreSite 2880 532980 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_141 CoreSite 2880 536760 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_142 CoreSite 2880 540540 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_143 CoreSite 2880 544320 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_144 CoreSite 2880 548100 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_145 CoreSite 2880 551880 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_146 CoreSite 2880 555660 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_147 CoreSite 2880 559440 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_148 CoreSite 2880 563220 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_149 CoreSite 2880 567000 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_150 CoreSite 2880 570780 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_151 CoreSite 2880 574560 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_152 CoreSite 2880 578340 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_153 CoreSite 2880 582120 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_154 CoreSite 2880 585900 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_155 CoreSite 2880 589680 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_156 CoreSite 2880 593460 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_157 CoreSite 2880 597240 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_158 CoreSite 2880 601020 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_159 CoreSite 2880 604800 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_160 CoreSite 2880 608580 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_161 CoreSite 2880 612360 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_162 CoreSite 2880 616140 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_163 CoreSite 2880 619920 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_164 CoreSite 2880 623700 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_165 CoreSite 2880 627480 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_166 CoreSite 2880 631260 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_167 CoreSite 2880 635040 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_168 CoreSite 2880 638820 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_169 CoreSite 2880 642600 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_170 CoreSite 2880 646380 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_171 CoreSite 2880 650160 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_172 CoreSite 2880 653940 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_173 CoreSite 2880 657720 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_174 CoreSite 2880 661500 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_175 CoreSite 2880 665280 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_176 CoreSite 2880 669060 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_177 CoreSite 2880 672840 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_178 CoreSite 2880 676620 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_179 CoreSite 2880 680400 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_180 CoreSite 2880 684180 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_181 CoreSite 2880 687960 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_182 CoreSite 2880 691740 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_183 CoreSite 2880 695520 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_184 CoreSite 2880 699300 N DO 2674 BY 1 STEP 480 0 ;
|
||||
ROW ROW_185 CoreSite 2880 703080 FS DO 2674 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 2685 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 2685 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 2685 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 2685 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 565 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 710140 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 710140 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 710140 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 710140 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 710140 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 710140 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 710140 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 710140 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 710140 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 710140 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 710140 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 710140 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 710140 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 710140 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 710140 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 710140 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 710140 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 710140 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 710140 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 710140 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 710140 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 710140 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 710140 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 710140 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 710140 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 710140 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 710140 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 710140 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 710140 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 710140 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 710140 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 710140 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 710140 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 710140 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 710140 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 710140 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 710140 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 710140 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 710140 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 710140 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 710140 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 710140 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 710140 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,323 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 1724160 313740 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 3580 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 3591 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 3591 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 3591 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 3591 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 756 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 313240 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 313240 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 313240 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 313240 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 313240 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 313240 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 313240 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 313240 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 313240 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 313240 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 313240 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 313240 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 313240 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 313240 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 313240 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 313240 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 313240 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 313240 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 313240 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 313240 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 313240 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 313240 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 313240 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 313240 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 313240 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 313240 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 313240 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 313240 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 313240 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 313240 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 313240 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 313240 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 313240 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 313240 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 313240 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 313240 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 313240 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 313240 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 313240 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 313240 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 313240 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 313240 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 313240 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,428 @@
|
||||
VERSION 5.8 ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
DESIGN tt_um_template ;
|
||||
UNITS DISTANCE MICRONS 1000 ;
|
||||
DIEAREA ( 0 0 ) ( 1724160 710640 ) ;
|
||||
ROW ROW_0 CoreSite 2880 3780 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_1 CoreSite 2880 7560 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_2 CoreSite 2880 11340 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_3 CoreSite 2880 15120 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_4 CoreSite 2880 18900 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_5 CoreSite 2880 22680 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_6 CoreSite 2880 26460 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_7 CoreSite 2880 30240 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_8 CoreSite 2880 34020 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_9 CoreSite 2880 37800 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_10 CoreSite 2880 41580 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_11 CoreSite 2880 45360 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_12 CoreSite 2880 49140 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_13 CoreSite 2880 52920 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_14 CoreSite 2880 56700 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_15 CoreSite 2880 60480 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_16 CoreSite 2880 64260 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_17 CoreSite 2880 68040 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_18 CoreSite 2880 71820 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_19 CoreSite 2880 75600 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_20 CoreSite 2880 79380 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_21 CoreSite 2880 83160 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_22 CoreSite 2880 86940 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_23 CoreSite 2880 90720 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_24 CoreSite 2880 94500 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_25 CoreSite 2880 98280 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_26 CoreSite 2880 102060 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_27 CoreSite 2880 105840 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_28 CoreSite 2880 109620 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_29 CoreSite 2880 113400 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_30 CoreSite 2880 117180 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_31 CoreSite 2880 120960 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_32 CoreSite 2880 124740 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_33 CoreSite 2880 128520 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_34 CoreSite 2880 132300 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_35 CoreSite 2880 136080 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_36 CoreSite 2880 139860 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_37 CoreSite 2880 143640 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_38 CoreSite 2880 147420 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_39 CoreSite 2880 151200 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_40 CoreSite 2880 154980 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_41 CoreSite 2880 158760 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_42 CoreSite 2880 162540 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_43 CoreSite 2880 166320 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_44 CoreSite 2880 170100 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_45 CoreSite 2880 173880 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_46 CoreSite 2880 177660 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_47 CoreSite 2880 181440 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_48 CoreSite 2880 185220 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_49 CoreSite 2880 189000 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_50 CoreSite 2880 192780 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_51 CoreSite 2880 196560 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_52 CoreSite 2880 200340 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_53 CoreSite 2880 204120 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_54 CoreSite 2880 207900 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_55 CoreSite 2880 211680 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_56 CoreSite 2880 215460 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_57 CoreSite 2880 219240 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_58 CoreSite 2880 223020 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_59 CoreSite 2880 226800 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_60 CoreSite 2880 230580 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_61 CoreSite 2880 234360 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_62 CoreSite 2880 238140 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_63 CoreSite 2880 241920 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_64 CoreSite 2880 245700 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_65 CoreSite 2880 249480 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_66 CoreSite 2880 253260 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_67 CoreSite 2880 257040 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_68 CoreSite 2880 260820 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_69 CoreSite 2880 264600 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_70 CoreSite 2880 268380 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_71 CoreSite 2880 272160 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_72 CoreSite 2880 275940 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_73 CoreSite 2880 279720 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_74 CoreSite 2880 283500 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_75 CoreSite 2880 287280 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_76 CoreSite 2880 291060 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_77 CoreSite 2880 294840 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_78 CoreSite 2880 298620 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_79 CoreSite 2880 302400 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_80 CoreSite 2880 306180 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_81 CoreSite 2880 309960 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_82 CoreSite 2880 313740 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_83 CoreSite 2880 317520 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_84 CoreSite 2880 321300 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_85 CoreSite 2880 325080 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_86 CoreSite 2880 328860 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_87 CoreSite 2880 332640 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_88 CoreSite 2880 336420 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_89 CoreSite 2880 340200 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_90 CoreSite 2880 343980 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_91 CoreSite 2880 347760 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_92 CoreSite 2880 351540 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_93 CoreSite 2880 355320 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_94 CoreSite 2880 359100 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_95 CoreSite 2880 362880 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_96 CoreSite 2880 366660 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_97 CoreSite 2880 370440 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_98 CoreSite 2880 374220 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_99 CoreSite 2880 378000 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_100 CoreSite 2880 381780 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_101 CoreSite 2880 385560 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_102 CoreSite 2880 389340 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_103 CoreSite 2880 393120 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_104 CoreSite 2880 396900 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_105 CoreSite 2880 400680 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_106 CoreSite 2880 404460 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_107 CoreSite 2880 408240 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_108 CoreSite 2880 412020 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_109 CoreSite 2880 415800 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_110 CoreSite 2880 419580 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_111 CoreSite 2880 423360 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_112 CoreSite 2880 427140 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_113 CoreSite 2880 430920 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_114 CoreSite 2880 434700 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_115 CoreSite 2880 438480 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_116 CoreSite 2880 442260 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_117 CoreSite 2880 446040 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_118 CoreSite 2880 449820 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_119 CoreSite 2880 453600 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_120 CoreSite 2880 457380 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_121 CoreSite 2880 461160 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_122 CoreSite 2880 464940 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_123 CoreSite 2880 468720 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_124 CoreSite 2880 472500 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_125 CoreSite 2880 476280 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_126 CoreSite 2880 480060 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_127 CoreSite 2880 483840 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_128 CoreSite 2880 487620 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_129 CoreSite 2880 491400 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_130 CoreSite 2880 495180 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_131 CoreSite 2880 498960 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_132 CoreSite 2880 502740 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_133 CoreSite 2880 506520 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_134 CoreSite 2880 510300 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_135 CoreSite 2880 514080 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_136 CoreSite 2880 517860 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_137 CoreSite 2880 521640 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_138 CoreSite 2880 525420 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_139 CoreSite 2880 529200 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_140 CoreSite 2880 532980 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_141 CoreSite 2880 536760 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_142 CoreSite 2880 540540 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_143 CoreSite 2880 544320 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_144 CoreSite 2880 548100 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_145 CoreSite 2880 551880 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_146 CoreSite 2880 555660 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_147 CoreSite 2880 559440 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_148 CoreSite 2880 563220 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_149 CoreSite 2880 567000 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_150 CoreSite 2880 570780 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_151 CoreSite 2880 574560 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_152 CoreSite 2880 578340 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_153 CoreSite 2880 582120 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_154 CoreSite 2880 585900 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_155 CoreSite 2880 589680 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_156 CoreSite 2880 593460 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_157 CoreSite 2880 597240 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_158 CoreSite 2880 601020 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_159 CoreSite 2880 604800 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_160 CoreSite 2880 608580 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_161 CoreSite 2880 612360 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_162 CoreSite 2880 616140 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_163 CoreSite 2880 619920 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_164 CoreSite 2880 623700 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_165 CoreSite 2880 627480 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_166 CoreSite 2880 631260 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_167 CoreSite 2880 635040 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_168 CoreSite 2880 638820 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_169 CoreSite 2880 642600 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_170 CoreSite 2880 646380 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_171 CoreSite 2880 650160 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_172 CoreSite 2880 653940 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_173 CoreSite 2880 657720 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_174 CoreSite 2880 661500 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_175 CoreSite 2880 665280 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_176 CoreSite 2880 669060 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_177 CoreSite 2880 672840 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_178 CoreSite 2880 676620 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_179 CoreSite 2880 680400 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_180 CoreSite 2880 684180 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_181 CoreSite 2880 687960 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_182 CoreSite 2880 691740 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_183 CoreSite 2880 695520 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_184 CoreSite 2880 699300 N DO 3580 BY 1 STEP 480 0 ;
|
||||
ROW ROW_185 CoreSite 2880 703080 FS DO 3580 BY 1 STEP 480 0 ;
|
||||
TRACKS X 480 DO 3591 STEP 480 LAYER Metal1 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal1 ;
|
||||
TRACKS X 480 DO 3591 STEP 480 LAYER Metal2 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal2 ;
|
||||
TRACKS X 480 DO 3591 STEP 480 LAYER Metal3 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal3 ;
|
||||
TRACKS X 480 DO 3591 STEP 480 LAYER Metal4 ;
|
||||
TRACKS Y 420 DO 1691 STEP 420 LAYER Metal4 ;
|
||||
TRACKS X 1640 DO 756 STEP 2280 LAYER TopMetal1 ;
|
||||
TRACKS Y 1640 DO 311 STEP 2280 LAYER TopMetal1 ;
|
||||
COMPONENTS 0 ;
|
||||
END COMPONENTS
|
||||
PINS 43 ;
|
||||
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 187200 710140 ) N ;
|
||||
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 191040 710140 ) N ;
|
||||
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 183360 710140 ) N ;
|
||||
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 179520 710140 ) N ;
|
||||
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 175680 710140 ) N ;
|
||||
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 171840 710140 ) N ;
|
||||
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 168000 710140 ) N ;
|
||||
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 164160 710140 ) N ;
|
||||
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 160320 710140 ) N ;
|
||||
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 156480 710140 ) N ;
|
||||
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 152640 710140 ) N ;
|
||||
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 148800 710140 ) N ;
|
||||
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 144960 710140 ) N ;
|
||||
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 141120 710140 ) N ;
|
||||
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 137280 710140 ) N ;
|
||||
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 133440 710140 ) N ;
|
||||
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 129600 710140 ) N ;
|
||||
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 125760 710140 ) N ;
|
||||
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 121920 710140 ) N ;
|
||||
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 56640 710140 ) N ;
|
||||
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 52800 710140 ) N ;
|
||||
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 48960 710140 ) N ;
|
||||
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 45120 710140 ) N ;
|
||||
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 41280 710140 ) N ;
|
||||
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 37440 710140 ) N ;
|
||||
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 33600 710140 ) N ;
|
||||
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 29760 710140 ) N ;
|
||||
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 87360 710140 ) N ;
|
||||
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 83520 710140 ) N ;
|
||||
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 79680 710140 ) N ;
|
||||
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 75840 710140 ) N ;
|
||||
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 72000 710140 ) N ;
|
||||
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 68160 710140 ) N ;
|
||||
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 64320 710140 ) N ;
|
||||
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 60480 710140 ) N ;
|
||||
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 118080 710140 ) N ;
|
||||
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 114240 710140 ) N ;
|
||||
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 110400 710140 ) N ;
|
||||
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 106560 710140 ) N ;
|
||||
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 102720 710140 ) N ;
|
||||
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 98880 710140 ) N ;
|
||||
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 95040 710140 ) N ;
|
||||
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
|
||||
+ PLACED ( 91200 710140 ) N ;
|
||||
END PINS
|
||||
SPECIALNETS 2 ;
|
||||
- VGND + USE GROUND ;
|
||||
- VPWR + USE POWER ;
|
||||
END SPECIALNETS
|
||||
NETS 43 ;
|
||||
- clk ( PIN clk ) + USE SIGNAL ;
|
||||
- ena ( PIN ena ) + USE SIGNAL ;
|
||||
- rst_n ( PIN rst_n ) + USE SIGNAL ;
|
||||
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
|
||||
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
|
||||
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
|
||||
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
|
||||
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
|
||||
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
|
||||
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
|
||||
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
|
||||
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
|
||||
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
|
||||
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
|
||||
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
|
||||
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
|
||||
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
|
||||
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
|
||||
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
|
||||
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
|
||||
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
|
||||
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
|
||||
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
|
||||
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
|
||||
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
|
||||
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
|
||||
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
|
||||
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
|
||||
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
|
||||
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
|
||||
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
|
||||
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
|
||||
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
|
||||
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
|
||||
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
|
||||
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
|
||||
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
|
||||
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
|
||||
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
|
||||
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
|
||||
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
|
||||
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
|
||||
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
|
||||
END NETS
|
||||
END DESIGN
|
||||
@@ -0,0 +1,17 @@
|
||||
1x1: "0 0 202.08 154.98"
|
||||
1x2: "0 0 202.08 313.74"
|
||||
2x1: "0 0 419.52 154.98"
|
||||
2x2: "0 0 419.52 313.74"
|
||||
3x1: "0 0 636.96 154.98"
|
||||
3x2: "0 0 636.96 313.74"
|
||||
3x4: "0 0 636.96 710.64"
|
||||
4x1: "0 0 854.40 154.98"
|
||||
4x2: "0 0 854.40 313.74"
|
||||
4x4: "0 0 854.40 710.64"
|
||||
5x4: "0 0 1071.84 710.64"
|
||||
6x1: "0 0 1289.28 154.98"
|
||||
6x2: "0 0 1289.28 313.74"
|
||||
6x4: "0 0 1289.28 710.64"
|
||||
8x1: "0 0 1724.16 154.98"
|
||||
8x2: "0 0 1724.16 313.74"
|
||||
8x4: "0 0 1724.16 710.64"
|
||||
Binary file not shown.
@@ -0,0 +1,272 @@
|
||||
VERSION 5.7 ;
|
||||
NOWIREEXTENSIONATPIN ON ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
MACRO tt_logo_corner
|
||||
CLASS BLOCK ;
|
||||
FOREIGN tt_logo_corner ;
|
||||
ORIGIN 0.000 0.000 ;
|
||||
SIZE 100.000 BY 100.000 ;
|
||||
OBS
|
||||
LAYER TopMetal1 ;
|
||||
RECT 45.000 99.500 55.000 100.000 ;
|
||||
RECT 41.500 99.000 58.500 99.500 ;
|
||||
RECT 39.000 98.500 61.000 99.000 ;
|
||||
RECT 37.000 98.000 63.000 98.500 ;
|
||||
RECT 35.000 97.500 65.000 98.000 ;
|
||||
RECT 33.500 97.000 66.500 97.500 ;
|
||||
RECT 32.500 96.500 67.500 97.000 ;
|
||||
RECT 31.000 96.000 69.000 96.500 ;
|
||||
RECT 30.000 95.500 70.000 96.000 ;
|
||||
RECT 29.000 95.000 71.000 95.500 ;
|
||||
RECT 28.000 94.500 72.500 95.000 ;
|
||||
RECT 26.500 94.000 73.000 94.500 ;
|
||||
RECT 26.000 93.500 74.000 94.000 ;
|
||||
RECT 25.000 93.000 75.000 93.500 ;
|
||||
RECT 24.000 92.500 76.000 93.000 ;
|
||||
RECT 23.500 92.000 47.000 92.500 ;
|
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RECT 45.000 0.000 55.000 0.500 ;
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||||
END
|
||||
END tt_logo_corner
|
||||
END LIBRARY
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
`default_nettype none
|
||||
|
||||
module tt_logo_corner ();
|
||||
endmodule
|
||||
Reference in New Issue
Block a user