mirror of
https://github.com/TinyTapeout/tt-support-tools.git
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feat: add ihp-sg13cmos5l PDK alongside ihp-sg13g2
Based on work done in the ihp-sg13cmos5l branch
This commit is contained in:
Uri Shaked
@@ -0,0 +1,247 @@
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{
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"a21o" : {
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"description" : "2-input AND into first input of 2-input OR.",
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"doc_name": "AO21x",
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"doc_ref" : 7
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},
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"a21oi" : {
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"description" : "2-input AND into first input of 2-input NOR.",
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"doc_name": "A21OIx",
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"doc_ref" : 1
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},
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"a221oi" : {
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"description" : "2-input AND into first two inputs of 3-input NOR.",
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"doc_name": "A221OI",
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"doc_ref" : 2
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},
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"a22oi" : {
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"description" : "2-input AND into both inputs of 2-input NOR.",
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"doc_name": "A22OI",
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"doc_ref" : 3
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},
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"and2" : {
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"description" : "2-input AND.",
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"doc_name": "AND2x",
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"doc_ref" : 4
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},
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"and3" : {
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"description" : "3-input AND.",
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"doc_name": "AND3x",
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"doc_ref" : 5
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},
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"and4" : {
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"description" : "4-input AND.",
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"doc_name": "AND4x",
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"doc_ref" : 6
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},
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"antennanp" : {
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"description" : "Antenna tie-down diode.",
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"doc_name": "NP_ANT",
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"doc_ref" : 38
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},
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"buf" : {
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"description" : "Buffer.",
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"doc_name": "BUx",
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"doc_ref" : 9
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},
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"decap" : {
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"description" : "Decoupling capacitance filler.",
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"doc_name": "DECAPx",
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"doc_ref" : 10
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},
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"dfrbp" : {
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"description" : "Delay flop, inverted reset, complementary outputs.",
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"doc_name": "DFFRRx",
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"doc_ref" : 11
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},
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"dfrbpq": {
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"description" : "Delay flop, inverted reset, single output.",
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"doc_name": "DFRBPQx",
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"doc_ref" : 0
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},
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"dlhq" : {
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"description" : "Delay latch, non-inverted enable, single output.",
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"doc_name": "DLHQ",
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"doc_ref" : 12
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},
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"dlhr" : {
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"description" : "Delay latch, inverted reset, non-inverted enable, complementary outputs.",
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"doc_name": "DLHR",
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"doc_ref" : 14
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},
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"dlhrq" : {
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"description" : "Delay latch, inverted reset, non-inverted enable, single output.",
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"doc_name": "DLHRQ",
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"doc_ref" : 13
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},
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"dllr" : {
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"description" : "Delay latch, inverted reset, inverted enable, complementary outputs.",
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"doc_name": "DLLR",
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"doc_ref" : 16
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},
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"dllrq" : {
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"description" : "Delay latch, inverted reset, inverted enable, single output.",
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"doc_name": "DLLRQ",
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"doc_ref" : 15
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},
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"dlygate4sd1" : {
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"description" : "Delay Buffer 4-stage ... length inner stage gates.",
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"doc_name": "DLY1",
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"doc_ref" : 17
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},
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"dlygate4sd2" : {
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"description" : "Delay Buffer 4-stage ... length inner stage gates.",
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"doc_name": "DLY2",
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"doc_ref" : 18
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},
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"dlygate4sd3" : {
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"description" : "Delay Buffer 4-stage ... length inner stage gates.",
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"doc_name": "DLY4",
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"doc_ref" : 19
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},
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"ebufn" : {
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"description" : "Tri-state buffer, negative enable.",
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"doc_name": "BTLx",
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"doc_ref" : 8
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},
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"einvn" : {
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"description" : "Tri-state inverter, negative enable.",
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"doc_name": "EINVINx, ITL",
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"doc_ref" : 20
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},
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"fill" : {
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"description" : "Fill cell.",
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"doc_name": "FILLx",
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"doc_ref" : 21
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},
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"inv" : {
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"description" : "Inverter.",
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"doc_name": "INx",
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"doc_ref" : 23
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},
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"lgcp" : {
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"description" : "Clock gate.",
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"doc_name": "GCLK",
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"doc_ref" : 22
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},
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"mux2" : {
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"description" : "2-input multiplexer.",
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"doc_name": "MUX2x",
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"doc_ref" : 26
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},
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"mux4" : {
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"description" : "4-input multiplexer.",
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"doc_name": "MUX4",
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"doc_ref" : 27
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},
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"nand2" : {
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"description" : "2-input NAND.",
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"doc_name": "NAND2x",
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"doc_ref" : 30
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},
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"nand2b" : {
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"description" : "2-input NAND, first input inverted.",
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"doc_name": "NAND2B1, NAND2B2",
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"doc_ref" : 28
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},
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"nand3" : {
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"description" : "3-input NAND.",
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"doc_name": "NAND3",
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"doc_ref" : 32
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},
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"nand3b" : {
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"description" : "3-input NAND, first input inverted.",
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"doc_name": "NAND3B1",
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"doc_ref" : 31
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},
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"nand4" : {
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"description" : "4-input NAND.",
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"doc_name": "NAND4",
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"doc_ref" : 33
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},
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"nor2" : {
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"description" : "2-input NOR.",
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"doc_name": "NOR2x",
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"doc_ref" : 35
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},
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"nor2b" : {
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"description" : "2-input NOR, first input inverted.",
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"doc_name": "NOR2Bx",
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"doc_ref" : 34
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},
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"nor3" : {
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"description" : "3-input NOR.",
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"doc_name": "NOR3x",
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"doc_ref" : 36
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},
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"nor4" : {
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"description" : "4-input NOR.",
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"doc_name": "NOR4x",
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"doc_ref" : 37
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},
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"o21ai" : {
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"description" : "2-input OR into first input of 2-input NAND.",
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"doc_name": "O21AI",
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"doc_ref" : 39
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},
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"or2" : {
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"description" : "2-input OR.",
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"doc_name": "OR2x",
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"doc_ref" : 40
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},
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"or3" : {
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"description" : "3-input OR.",
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"doc_name": "OR3x",
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"doc_ref" : 41
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},
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"or4" : {
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"description" : "4-input OR.",
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"doc_name": "OR4x",
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"doc_ref" : 42
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},
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"sdfbbp" : {
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"description" : "Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.",
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"doc_name": "SDFRRS",
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"doc_ref" : 43
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},
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"sdfrbp": {
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"description" : "Scan delay flop, inverted reset, non-inverted clock, complementary outputs.",
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"doc_name": "SDFRBPx",
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"doc_ref" : 0
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},
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"sdfrbpq": {
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"description" : "Scan delay flop, inverted reset, non-inverted clock, single output.",
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"doc_name": "SDFRBPQx",
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"doc_ref" : 0
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},
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"sighold" : {
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"description" : "Cross-coupled inverters.",
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"doc_name": "KEEPSTATE",
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"doc_ref" : 25
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},
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"slgcp" : {
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"description" : "Scan gated clock.",
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"doc_name": "SGCLK",
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"doc_ref" : 44
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},
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"tiehi" : {
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"description" : "Constant high output.",
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"doc_name": "TIE1",
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"doc_ref" : 46
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},
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"tielo" : {
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"description" : "Constant low output.",
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"doc_name": "TIE0",
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"doc_ref" : 45
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},
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"xnor2" : {
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"description" : "2-input exclusive NOR.",
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"doc_name": "XNOR2_1",
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"doc_ref" : 47
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},
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"xor2" : {
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"description" : "2-input exclusive OR.",
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"doc_name": "XOR2_1",
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"doc_ref" : 48
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}
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}
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