TT06+ asic sim support, prelim

fpga/tt_fpga_fabricfox.pcf

@@ -0,0 +1,40 @@
+# Pinmap for the FabricFox version (TT06+) of TT ASIC SIMULATOR version 1.0
+
+# clock (both project and SPI clock)
+set_io -nowarn clk   20
+
+# project reset
+set_io -nowarn rst_n 37
+
+# RGB LED
+set_io -nowarn rgb[0] 39
+set_io -nowarn rgb[1] 40
+set_io -nowarn rgb[2] 41
+
+# I/O
+set_io -nowarn ui_in[0] 18
+set_io -nowarn ui_in[1] 19
+set_io -nowarn ui_in[2] 25
+set_io -nowarn ui_in[3] 26
+set_io -nowarn ui_in[4] 27
+set_io -nowarn ui_in[5] 28
+set_io -nowarn ui_in[6] 23
+set_io -nowarn ui_in[7] 31
+
+set_io -nowarn uio[0] 38
+set_io -nowarn uio[1] 36
+set_io -nowarn uio[2] 42
+set_io -nowarn uio[3] 43
+set_io -nowarn uio[4] 44
+set_io -nowarn uio[5] 45
+set_io -nowarn uio[6] 47
+set_io -nowarn uio[7] 46
+
+set_io -nowarn uo_out[0] 2
+set_io -nowarn uo_out[1] 48
+set_io -nowarn uo_out[2] 4
+set_io -nowarn uo_out[3] 3
+set_io -nowarn uo_out[4] 9
+set_io -nowarn uo_out[5] 6
+set_io -nowarn uo_out[6] 11
+set_io -nowarn uo_out[7] 10

project.py

@@ -585,8 +585,28 @@ class Project:
     def run_lvs(self):
         logging.warning("LVS is already included in OpenLane hardening job, skipping")
 
-    def create_fpga_bitstream(self):
+    def create_fpga_bitstream(self, args):
         logging.info(f"Creating FPGA bitstream for {self}")
+        
+        target_map = {
+            'classic': {
+                    'pcf': 'tt_fpga_top.pcf',
+                    'def_name': 'tt_fpga',
+            },
+            
+            'fabricfox': {
+            
+                    'pcf': 'tt_fpga_fabricfox.pcf',
+                    'def_name': 'tt_ff_fpga'
+            }
+        
+        }
+        pcf_file = target_map[args.fpga_breakout_target]['pcf']
+        
+        base_name = args.fpga_bitstream_name
+        if not len(base_name):
+            base_name = target_map[args.fpga_breakout_target]['def_name']
+        
 
         with open(os.path.join(SCRIPT_DIR, "fpga/tt_fpga_top.v"), "r") as f:
             top_module_template = f.read()
@@ -602,7 +622,7 @@ class Project:
         sources = [os.path.join(self.src_dir, src) for src in self.sources]
         source_list = " ".join(sources)
 
-        yosys_cmd = f"yosys -l {build_dir}/01-synth.log -DSYNTH -p 'synth_ice40 -top tt_fpga_top -json {build_dir}/tt_fpga.json' src/_tt_fpga_top.v {source_list}"
+        yosys_cmd = f"yosys -l {build_dir}/01-synth.log -DSYNTH -p 'synth_ice40 -top tt_fpga_top -json {build_dir}/{base_name}.json' src/_tt_fpga_top.v {source_list}"
         logging.debug(yosys_cmd)
         p = subprocess.run(yosys_cmd, shell=True)
         if p.returncode != 0:
@@ -612,21 +632,21 @@ class Project:
         seed = os.getenv("TT_FPGA_SEED", "10")
         freq = os.getenv("TT_FPGA_FREQ", "12")
 
-        nextpnr_cmd = f"nextpnr-ice40 -l {build_dir}/02-nextpnr.log --pcf-allow-unconstrained --seed {seed} --freq {freq} --package sg48 --up5k --asc {build_dir}/tt_fpga.asc --pcf {SCRIPT_DIR}/fpga/tt_fpga_top.pcf --json {build_dir}/tt_fpga.json"
+        nextpnr_cmd = f"nextpnr-ice40 -l {build_dir}/02-nextpnr.log --pcf-allow-unconstrained --seed {seed} --freq {freq} --package sg48 --up5k --asc {build_dir}/{base_name}.asc --pcf {SCRIPT_DIR}/fpga/{pcf_file} --json {build_dir}/{base_name}.json"
         logging.debug(nextpnr_cmd)
         p = subprocess.run(nextpnr_cmd, shell=True)
         if p.returncode != 0:
             logging.error("placement failed")
             exit(1)
 
-        icepack_cmd = f"icepack {build_dir}/tt_fpga.asc {build_dir}/tt_fpga.bin"
+        icepack_cmd = f"icepack {build_dir}/{base_name}.asc {build_dir}/{base_name}.bin"
         logging.debug(icepack_cmd)
         p = subprocess.run(icepack_cmd, shell=True)
         if p.returncode != 0:
             logging.error("bitstream creation failed failed")
             exit(1)
 
-        logging.info(f"Bitstream created successfully: {build_dir}/tt_fpga.bin")
+        logging.info(f"Bitstream created successfully: {build_dir}/{base_name}.bin")
 
     # doc check
     # makes sure that the basic info is present

tt_tool.py

@@ -118,6 +118,17 @@ if __name__ == "__main__":
         action="store_const",
         const=True,
     )
+    parser.add_argument(
+        "--fpga-breakout-target",
+        help="Select target breakout: classic (TT04) or fabricfox (TT06+)",
+        choices=["classic", "fabricfox"],
+        default="classic",
+    )
+    parser.add_argument(
+        "--fpga-bitstream-name",
+        help="Set the bitstream name",
+        default="",
+    )
 
     args = parser.parse_args()
 
@@ -174,4 +185,4 @@ if __name__ == "__main__":
         project.create_svg()
 
     if args.create_fpga_bitstream:
-        project.create_fpga_bitstream()
+        project.create_fpga_bitstream(args)