mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-02 20:26:10 +01:00
refactor(tt_tool): openlane2 -> librelane
This commit is contained in:
@@ -23,6 +23,6 @@ pre-commit install
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## Configuration
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* creates a little TCL shim that tells OpenLane where the source is and the name of the top module
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* creates a little TCL shim that tells LibreLane where the source is and the name of the top module
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* makes sure the top module is not called 'top'
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* if you have OpenLane installed locally, then you can harden the design with --harden
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* if you have LibreLane installed locally, then you can harden the design with --harden
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+4
-12
@@ -523,7 +523,7 @@ class Project:
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arg_progress = "--hide-progress-bar" if "CI" in os.environ else ""
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arg_pdk_root = '--pdk-root "$PDK_ROOT"' if "PDK_ROOT" in os.environ else ""
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arg_pdk = "--manual-pdk --pdk ihp-sg13g2" if self.ihp else ""
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harden_cmd = f"python -m openlane {arg_pdk_root} --docker-no-tty --dockerized {arg_pdk_root} {arg_pdk} --run-tag wokwi --force-run-dir runs/wokwi {arg_progress} src/config_merged.json"
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harden_cmd = f"python -m librelane {arg_pdk_root} --docker-no-tty --dockerized {arg_pdk_root} {arg_pdk} --run-tag wokwi --force-run-dir runs/wokwi {arg_progress} src/config_merged.json"
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env = os.environ.copy()
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logging.debug(harden_cmd)
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p = subprocess.run(harden_cmd, shell=True, env=env)
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@@ -548,7 +548,7 @@ class Project:
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resolved_json_path = "runs/wokwi/resolved.json"
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config = json.load(open(os.path.join(self.local_dir, resolved_json_path)))
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openlane_version = config["meta"]["openlane_version"]
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librelane_version = config["meta"]["librelane_version"]
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if self.ihp:
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pdk_repo = Repo(env["PDK_ROOT"])
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pdk_repo_name = list(pdk_repo.remotes[0].urls)[0].split("/")[-1]
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@@ -559,9 +559,7 @@ class Project:
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config["PDK_ROOT"], config["PDK"], "SOURCES"
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)
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pdk_sources = open(pdk_sources_file).read()
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open("runs/wokwi/OPENLANE_VERSION", "w").write(
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f"OpenLane2 {openlane_version}\n"
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)
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open("runs/wokwi/FLOW_VERSION", "w").write(f"LibreLane {librelane_version}\n")
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open("runs/wokwi/PDK_SOURCES", "w").write(pdk_sources)
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if not self.ihp:
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volare.enable(
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@@ -572,12 +570,6 @@ class Project:
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os.chdir(cwd)
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def run_drc(self):
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logging.warning("DRC is already included in OpenLane hardening job, skipping")
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def run_lvs(self):
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logging.warning("LVS is already included in OpenLane hardening job, skipping")
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def create_fpga_bitstream(self, args):
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logging.info(f"Creating FPGA bitstream for {self}")
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@@ -1009,7 +1001,7 @@ class Project:
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return num_cells
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# Parse the lib, cell and drive strength an OpenLane gate-level Verilog file
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# Parse the lib, cell and drive strength an LibreLane gate-level Verilog file
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def get_cell_counts_from_gl(self):
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cell_count: typing.Dict[str, int] = {}
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total = 0
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+1
-8
@@ -19,13 +19,6 @@ if __name__ == "__main__":
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const=logging.DEBUG,
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default=logging.INFO,
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)
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parser.add_argument(
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"--openlane2",
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help="use openlane 2",
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action="store_const",
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const=True,
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default=True,
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)
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parser.add_argument(
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"--ihp",
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help="use IHP PDK",
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@@ -106,7 +99,7 @@ if __name__ == "__main__":
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)
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parser.add_argument(
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"--harden",
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help="use a local OpenLane install to harden the project",
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help="use a local LibreLane install to harden the project",
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action="store_const",
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const=True,
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)
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