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feat(ihp-sg13cmos5l): analog project support

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This commit is contained in:
Uri Shaked
2026-10-29 21:32:06 +01:00
parent 02abf73b5f
commit 617676148e
7 changed files with 1519 additions and 3 deletions
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precheck/precheck.py
+1 -3
View File
@@ -460,8 +460,6 @@ def main():
pinout = yaml_data.get("pinout", {})
if uses_vapwr and not is_analog:
raise PrecheckFailure("Projects with VAPWR power need at least one analog pin")
if is_analog and tech == "ihp-sg13cmos5l":
raise PrecheckFailure("Analog projects are not supported on ihp-sg13cmos5l yet")
def_root = f"../tech/{tech}/def"
if is_analog:
analog_def = f"{def_root}/analog/tt_analog_{tiles}"
@@ -569,7 +567,7 @@ def main():
"check": lambda: analog_pin_check(
gds_file, tech, is_analog, uses_vapwr, analog_pins, pinout
),
"techs": ["sky130A", "ihp-sg13g2", "gf180mcuD"],
"techs": ["sky130A", "ihp-sg13g2", "ihp-sg13cmos5l", "gf180mcuD"],
},
{
"name": "Verilog syntax check",
precheck/tech_data.py
+11
View File
@@ -135,6 +135,17 @@ def analog_pin_rects(tech: str, uses_vapwr: bool):
x2, y2 = x1 + 1.75, y1 + 2.0
rect = ((x1, y1), (x2, y2))
yield (rect, pin_layer, via_layers)
elif tech == "ihp-sg13cmos5l":
pin_layer = (50, 0) # Metal4
via_layers = [(49, 0)] # Via3
for pin_number in range(8):
if uses_vapwr:
x1, y1 = 174.18 - 24.48 * pin_number, 0.0
else:
x1, y1 = 189.54 - 24.48 * pin_number, 0.0
x2, y2 = x1 + 3.0, y1 + 1.0
rect = ((x1, y1), (x2, y2))
yield (rect, pin_layer, via_layers)
elif tech == "gf180mcuD":
pin_layer = (46, 0) # Metal4
via_layers = [(40, 0)] # Via3
tech/ihp-sg13cmos5l/def/analog/magic_init_project.tcl
+55
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@@ -0,0 +1,55 @@
# SPDX-License-Identifier: Apache-2.0
# Copyright (c) 2024-2026 Tiny Tapeout LTD
# Author: Uri Shaked
# Description: This script initializes a new Magic project for an analog design on Tiny Tapeout.
# Important: before running this script, download the the .def file from
# https://raw.githubusercontent.com/TinyTapeout/tt-support-tools/main/tech/ihp-sg13cmos5l/def/analog/tt_analog_1x2.def
#
# SG13CMOS5L requires Magic 8.3.657 or newer.
# Change the settings below to match your design:
# ------------------------------------------------
set TOP_LEVEL_CELL tt_um_analog_example
set TEMPLATE_FILE tt_analog_1x2.def
set POWER_STRIPE_WIDTH 2.4um ;# The minimum width is 2.1um
# Power stripes: NET name, x position. You can add additional power stripes for each net, as needed.
# Keep the stripes at least 1um apart. Power stripes go on Metal4: TopMetal1 is reserved for the chip-level power grid.
set POWER_STRIPES {
VDPWR 1um
VGND 6um
}
# Read in the pin positions
# -------------------------
def read $TEMPLATE_FILE
cellname rename tt_um_template $TOP_LEVEL_CELL
# Draw the power stripes
# --------------------------------
proc draw_power_stripe {name x} {
global POWER_STRIPE_WIDTH
box $x 5um $x 308um
box width $POWER_STRIPE_WIDTH
paint met4
label $name FreeSans 0.25u -met4
port make
port use [expr {$name eq "VGND" ? "ground" : "power"}]
port class bidirectional
port connections n s e w
}
# You can extra power stripes, as you need.
foreach {name x} $POWER_STRIPES {
puts "Drawing power stripe $name at $x"
draw_power_stripe $name $x
}
# Save the layout and export GDS/LEF
# ----------------------------------
save ${TOP_LEVEL_CELL}.mag
file mkdir gds
gds write gds/${TOP_LEVEL_CELL}.gds
file mkdir lef
lef write lef/${TOP_LEVEL_CELL}.lef -hide -pinonly
tech/ihp-sg13cmos5l/def/analog/tt_analog_1x2.def
+363
View File
@@ -0,0 +1,363 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 202080 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 409 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 409 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 409 BY 1 STEP 480 0 ;
TRACKS X 420 DO 480 STEP 420 LAYER Metal1 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal2 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal2 ;
TRACKS X 420 DO 480 STEP 420 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 420 STEP 480 LAYER Metal4 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal4 ;
TRACKS X 1640 DO 88 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 51 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 191040 500 ) N ;
- ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 166560 500 ) N ;
- ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 142080 500 ) N ;
- ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 117600 500 ) N ;
- ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 93120 500 ) N ;
- ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 68640 500 ) N ;
- ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 44160 500 ) N ;
- ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 19680 500 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 51 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ua[0] ( PIN ua[0] ) + USE SIGNAL ;
- ua[1] ( PIN ua[1] ) + USE SIGNAL ;
- ua[2] ( PIN ua[2] ) + USE SIGNAL ;
- ua[3] ( PIN ua[3] ) + USE SIGNAL ;
- ua[4] ( PIN ua[4] ) + USE SIGNAL ;
- ua[5] ( PIN ua[5] ) + USE SIGNAL ;
- ua[6] ( PIN ua[6] ) + USE SIGNAL ;
- ua[7] ( PIN ua[7] ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
tech/ihp-sg13cmos5l/def/analog/tt_analog_1x2_pgvaa.def
+363
View File
@@ -0,0 +1,363 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 186720 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 377 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 377 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 377 BY 1 STEP 480 0 ;
TRACKS X 420 DO 444 STEP 420 LAYER Metal1 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
TRACKS X 480 DO 388 STEP 480 LAYER Metal2 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal2 ;
TRACKS X 420 DO 444 STEP 420 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 388 STEP 480 LAYER Metal4 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal4 ;
TRACKS X 1640 DO 81 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 51 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 175680 500 ) N ;
- ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 151200 500 ) N ;
- ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 126720 500 ) N ;
- ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 102240 500 ) N ;
- ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 77760 500 ) N ;
- ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 53280 500 ) N ;
- ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 28800 500 ) N ;
- ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 4320 500 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 37440 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33600 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 29760 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 25920 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 22080 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 18240 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 14400 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 51 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ua[0] ( PIN ua[0] ) + USE SIGNAL ;
- ua[1] ( PIN ua[1] ) + USE SIGNAL ;
- ua[2] ( PIN ua[2] ) + USE SIGNAL ;
- ua[3] ( PIN ua[3] ) + USE SIGNAL ;
- ua[4] ( PIN ua[4] ) + USE SIGNAL ;
- ua[5] ( PIN ua[5] ) + USE SIGNAL ;
- ua[6] ( PIN ua[6] ) + USE SIGNAL ;
- ua[7] ( PIN ua[7] ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
tech/ihp-sg13cmos5l/def/analog/tt_analog_2x2.def
+363
View File
@@ -0,0 +1,363 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 419520 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 862 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 862 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 862 BY 1 STEP 480 0 ;
TRACKS X 420 DO 998 STEP 420 LAYER Metal1 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal2 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal2 ;
TRACKS X 420 DO 998 STEP 420 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 873 STEP 480 LAYER Metal4 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal4 ;
TRACKS X 1640 DO 183 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 51 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 191040 500 ) N ;
- ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 166560 500 ) N ;
- ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 142080 500 ) N ;
- ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 117600 500 ) N ;
- ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 93120 500 ) N ;
- ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 68640 500 ) N ;
- ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 44160 500 ) N ;
- ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 19680 500 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 37440 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33600 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 29760 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 51 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ua[0] ( PIN ua[0] ) + USE SIGNAL ;
- ua[1] ( PIN ua[1] ) + USE SIGNAL ;
- ua[2] ( PIN ua[2] ) + USE SIGNAL ;
- ua[3] ( PIN ua[3] ) + USE SIGNAL ;
- ua[4] ( PIN ua[4] ) + USE SIGNAL ;
- ua[5] ( PIN ua[5] ) + USE SIGNAL ;
- ua[6] ( PIN ua[6] ) + USE SIGNAL ;
- ua[7] ( PIN ua[7] ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
tech/ihp-sg13cmos5l/def/analog/tt_analog_2x2_pgvaa.def
+363
View File
@@ -0,0 +1,363 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 404160 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 830 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 830 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 830 BY 1 STEP 480 0 ;
TRACKS X 420 DO 962 STEP 420 LAYER Metal1 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal1 ;
TRACKS X 480 DO 841 STEP 480 LAYER Metal2 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal2 ;
TRACKS X 420 DO 962 STEP 420 LAYER Metal3 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal3 ;
TRACKS X 480 DO 841 STEP 480 LAYER Metal4 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal4 ;
TRACKS X 1640 DO 177 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1640 DO 137 STEP 2280 LAYER TopMetal1 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 51 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ua[0] + NET ua[0] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 175680 500 ) N ;
- ua[1] + NET ua[1] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 151200 500 ) N ;
- ua[2] + NET ua[2] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 126720 500 ) N ;
- ua[3] + NET ua[3] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 102240 500 ) N ;
- ua[4] + NET ua[4] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 77760 500 ) N ;
- ua[5] + NET ua[5] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 53280 500 ) N ;
- ua[6] + NET ua[6] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 28800 500 ) N ;
- ua[7] + NET ua[7] + DIRECTION INOUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -1500 -500 ) ( 1500 500 )
+ PLACED ( 4320 500 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 37440 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33600 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 29760 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 25920 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 22080 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 18240 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 14400 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 51 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ua[0] ( PIN ua[0] ) + USE SIGNAL ;
- ua[1] ( PIN ua[1] ) + USE SIGNAL ;
- ua[2] ( PIN ua[2] ) + USE SIGNAL ;
- ua[3] ( PIN ua[3] ) + USE SIGNAL ;
- ua[4] ( PIN ua[4] ) + USE SIGNAL ;
- ua[5] ( PIN ua[5] ) + USE SIGNAL ;
- ua[6] ( PIN ua[6] ) + USE SIGNAL ;
- ua[7] ( PIN ua[7] ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN