feat: validate that top module name starts with "tt_um"

2026-11-03 12:46:08 +01:00 · 2023-05-27 17:35:54 +03:00
parent a4137038c4
commit 96362ae28e
1 changed files with 4 additions and 0 deletions
@@ -123,6 +123,10 @@ class Project():
            self.top_module             = f"tt_um_wokwi_{self.wokwi_id}"
            self.src_files              = self.get_wokwi_source()
            self.top_verilog_filename   = self.src_files[0]
+        
+        if not self.top_module.startswith("tt_um_"):
+            logging.error(f'top module name must start with "tt_um_" (current value: "{self.top_module}")')
+            exit(1)

        self.macro_instance         = f"{self.top_module}_{self.index :03}"