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fix: shuttle config fails as tt_um_chip_rom verilog is missing

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The Chip ROM is now auto generated, so the GL verilog only exists after we configure the shuttle
This commit is contained in:
Uri Shaked
2023-09-10 20:23:48 +03:00
parent cadbfbcd25
commit b02cc19e78
1 changed files with 2 additions and 0 deletions
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project.py
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@@ -44,6 +44,8 @@ class Project():
def check_ports(self): def check_ports(self):
top = self.get_macro_name() top = self.get_macro_name()
if not self.is_user_project and top == "tt_um_chip_rom":
return # Chip ROM is auto generated, so we don't have the verilog yet
sources = [os.path.join(self.src_dir, src) for src in self.src_files] sources = [os.path.join(self.src_dir, src) for src in self.src_files]
source_list = " ".join(sources) source_list = " ".join(sources)