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fix: shuttle config fails as tt_um_chip_rom verilog is missing
The Chip ROM is now auto generated, so the GL verilog only exists after we configure the shuttle
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@@ -44,6 +44,8 @@ class Project():
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def check_ports(self):
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def check_ports(self):
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top = self.get_macro_name()
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top = self.get_macro_name()
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if not self.is_user_project and top == "tt_um_chip_rom":
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return # Chip ROM is auto generated, so we don't have the verilog yet
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sources = [os.path.join(self.src_dir, src) for src in self.src_files]
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sources = [os.path.join(self.src_dir, src) for src in self.src_files]
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source_list = " ".join(sources)
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source_list = " ".join(sources)
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