working for mpw-9a

2026-11-03 04:36:09 +01:00 · 2023-03-16 09:41:11 +01:00
parent efb4dc5959
commit e882cdf915
6 changed files with 140 additions and 50 deletions
@@ -1,4 +1,5 @@
 import logging
+import json


 class CaravelConfig():
@@ -86,53 +87,34 @@ class CaravelConfig():

        logging.info(f"total user macros placed: {num_macros_placed}")

-        # macro_power.tcl: extra file for macro power hooks
-        logging.info("creating macro_power.tcl")
-        with open("openlane/user_project_wrapper/macro_power.tcl", 'w') as fh:
-            fh.write('set ::env(FP_PDN_MACRO_HOOKS) "\\\n')
-            fh.write("	")
-            fh.write("scan_controller")
-            fh.write(" vccd1 vssd1 vccd1 vssd1")
-            fh.write(", \\\n")
-            for i in range(self.num_projects):
-                fh.write("	")
-                fh.write(self.projects[i].get_scanchain_instance())
-                fh.write(" vccd1 vssd1 vccd1 vssd1, \\\n")
-                fh.write("	")
-                fh.write(self.projects[i].get_macro_instance())
-                fh.write(" vccd1 vssd1 vccd1 vssd1")
-                if i != self.num_projects - 1:
-                    fh.write(", \\\n")
-            fh.write('"\n')
+        with open("upw_config.json") as fh:
+            caravel_config = json.load(fh)

-        # extra_lef_gds.tcl
-        lefs = []
-        gdss = []
-        logging.info("creating extra_lef_gds.tcl")
+        power_domains = "vccd1 vssd1 vccd1 vssd1"
+        power_config = []
+        logging.info("creating macro hooks")
+
+        for i in range(self.num_projects):
+            power_config.append(f"{self.projects[i].get_scanchain_instance()} {power_domains},")
+            power_config.append(f"{self.projects[i].get_macro_instance()} {power_domains},")
+        power_config.append(f"scan_controller {power_domains}")  # no trailing comma
+
+        caravel_config["FP_PDN_MACRO_HOOKS"] = power_config
+
+        logging.info("GDS and LEF")
+        lef_prefix = "dir::../../lef/"
+        gds_prefix = "dir::../../gds/"
+        caravel_config["EXTRA_LEFS"].append(lef_prefix + "scan_controller.lef")
+        caravel_config["EXTRA_LEFS"].append(lef_prefix + "scanchain.lef")
+        caravel_config["EXTRA_GDS_FILES"].append(gds_prefix + "scan_controller.gds")
+        caravel_config["EXTRA_GDS_FILES"].append(gds_prefix + "scanchain.gds")
        for project in self.projects:
            if not project.is_fill():
-                lefs.append(project.get_macro_lef_filename())
-                gdss.append(project.get_macro_gds_filename())
+                caravel_config["EXTRA_LEFS"].append(lef_prefix + project.get_macro_lef_filename())
+                caravel_config["EXTRA_GDS_FILES"].append(gds_prefix + project.get_macro_gds_filename())

-        with open("openlane/user_project_wrapper/extra_lef_gds.tcl", 'w') as fh:
-            fh.write('set ::env(EXTRA_LEFS) "\\\n')
-            fh.write("$script_dir/../../lef/scan_controller.lef \\\n")
-            fh.write("$script_dir/../../lef/scanchain.lef \\\n")
-            for i, lef in enumerate(lefs):
-                fh.write("$script_dir/../../lef/{}".format(lef))
-                if i != len(lefs) - 1:
-                    fh.write(" \\\n")
-                else:
-                    fh.write('"\n')
-            fh.write('set ::env(EXTRA_GDS_FILES) "\\\n')
-            fh.write("$script_dir/../../gds/scan_controller.gds \\\n")
-            fh.write("$script_dir/../../gds/scanchain.gds \\\n")
-            for i, gds in enumerate(gdss):
-                fh.write("$script_dir/../../gds/{}".format(gds))
-                if i != len(gdss) - 1:
-                    fh.write(" \\\n")
-                else:
-                    fh.write('"\n')
+        with open("openlane/user_project_wrapper/config.json", 'w') as fh:
+            json.dump(caravel_config, fh, indent=4)

    # instantiate inside user_project_wrapper
    def instantiate(self):
@@ -1,4 +1,5 @@
 start_date: '2023-03-01'
+name: 'tt03' # used for university orders
 filler_project: https://github.com/TinyTapeout/tt03-test-invert
 project_dir: 'projects'
 tmp_dir: '/tmp/tt'
@@ -111,9 +111,9 @@ class Projects():
                if filler is False:
                    project.copy_files_to_caravel()

-                # check all top level module ports are correct
-                project.check_ports()
-                project.check_num_cells()
+                    # check all top level module ports are correct
+                    project.check_ports()
+                    project.check_num_cells()

            self.projects.append(project)

@@ -198,7 +198,7 @@ class Project():
                logging.error(f"{self.git_url} != {git_remote}")
                exit(1)
        else:
-            logging.info("clone")
+            logging.debug("clone")
            git.Repo.clone_from(self.git_url, self.local_dir, recursive=True)

    def pull(self):
@@ -24,12 +24,12 @@
  fill: false
 6:
  url: https://github.com/dgarrett/tt03-num-latch
-  status: disable
+  status: active
  fill: false
 7:
-  url: https://github.com/TinyTapeout/tt03-test-invert
+  url: https://github.com/MichaelBell/tt03-hovalaag
  status: active
-  fill: true
+  fill: false
 8:
  url: https://github.com/TinyTapeout/tt03-test-invert
  status: active
@@ -0,0 +1,107 @@
+{
+    "DESIGN_NAME": "user_project_wrapper",
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/user_project_wrapper.v"
+    ],
+    "ROUTING_CORES": 8,
+    "CLOCK_PERIOD": 25,
+    "CLOCK_PORT": "wb_clk_i",
+    "CLOCK_NET": "mprj.clk",
+    "FP_PDN_MACRO_HOOKS": [],
+    "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
+    "PDN_CFG": "dir::pdn_cfg.tcl",
+    "MAGIC_DEF_LABELS": 0,
+    "VERILOG_FILES_BLACKBOX": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/blackbox_project_includes.v"
+    ],
+    "EXTRA_LEFS": [],
+    "EXTRA_GDS_FILES": [],
+    "BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
+    "RUN_KLAYOUT_XOR": 0,
+    "RUN_KLAYOUT_DRC": 0,
+    "RUN_MAGIC_DRC": 0,
+    "IO_SYNC": 0,
+    "FP_PDN_CHECK_NODES": 0,
+    "SYNTH_ELABORATE_ONLY": 1,
+    "PL_RANDOM_GLB_PLACEMENT": 1,
+    "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
+    "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
+    "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
+    "FP_PDN_ENABLE_RAILS": 0,
+    "DIODE_INSERTION_STRATEGY": 0,
+    "RUN_FILL_INSERTION": 0,
+    "RUN_TAP_DECAP_INSERTION": 0,
+    "FP_PDN_VPITCH": 140,
+    "FP_PDN_VOFFSET": 186,
+    "FP_PDN_HPITCH": 185,
+    "FP_PDN_HOFFSET": 130,
+    "CLOCK_TREE_SYNTH": 0,
+    "MAGIC_ZEROIZE_ORIGIN": 0,
+    "FP_SIZING": "absolute",
+    "RUN_CVC": 0,
+    "UNIT": 2.4,
+    "FP_IO_VEXTEND": "expr::2 * $UNIT",
+    "FP_IO_HEXTEND": "expr::2 * $UNIT",
+    "FP_IO_VLENGTH": "expr::$UNIT",
+    "FP_IO_HLENGTH": "expr::$UNIT",
+    "FP_IO_VTHICKNESS_MULT": 4,
+    "FP_IO_HTHICKNESS_MULT": 4,
+    "FP_PDN_CORE_RING": 1,
+    "FP_PDN_CORE_RING_VWIDTH": 3.1,
+    "FP_PDN_CORE_RING_HWIDTH": 3.1,
+    "FP_PDN_CORE_RING_VOFFSET": 12.45,
+    "FP_PDN_CORE_RING_HOFFSET": 12.45,
+    "FP_PDN_CORE_RING_VSPACING": 1.7,
+    "FP_PDN_CORE_RING_HSPACING": 1.7,
+    "FP_PDN_VWIDTH": 3.1,
+    "FP_PDN_HWIDTH": 3.1,
+    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
+    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
+    "VDD_NETS": [
+        "vccd1",
+        "vccd2",
+        "vdda1",
+        "vdda2"
+    ],
+    "GND_NETS": [
+        "vssd1",
+        "vssd2",
+        "vssa1",
+        "vssa2"
+    ],
+    "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
+    "pdk::sky130*": {
+        "RT_MAX_LAYER": "met4",
+        "DIE_AREA": "0 0 2920 3520",
+        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 25
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "pdk::gf180mcuC": {
+        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+        "FP_PDN_CHECK_NODES": 0,
+        "FP_PDN_ENABLE_RAILS": 0,
+        "RT_MAX_LAYER": "Metal4",
+        "DIE_AREA": "0 0 3000 3000",
+        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
+        "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
+        "DIODE_INSERTION_STRATEGY": 0,
+        "MAGIC_WRITE_FULL_LEF": 0
+    }
+}