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feat: add experimental IHP support

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htfab
2024-09-24 22:23:12 +03:00
committed by Uri Shaked
parent dd77f85278
commit f8cc66a644
21 changed files with 4308 additions and 60 deletions
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ihp/categories.json
+67
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{
"categories" : [
"AND",
"OR",
"NAND",
"NOR",
"Clock",
"Flip Flops",
"Multiplexer",
"Latch",
"Inverter",
"Buffer",
"Fill",
"Tap",
"Diode",
"Combo Logic",
"Misc"
],
"map" : {
"a21o" : 13,
"a21oi" : 13,
"a22oi" : 13,
"a221oi" : 13,
"and2" : 0,
"and3" : 0,
"and4" : 0,
"antennanp" : 12,
"buf" : 9,
"decap" : 10,
"dfrbp" : 5,
"dlhq" : 7,
"dlhr" : 7,
"dlhrq" : 7,
"dllr" : 7,
"dllrq" : 7,
"dlygate4sd1" : 14,
"dlygate4sd2" : 14,
"dlygate4sd3" : 14,
"ebufn" : 14,
"einvn" : 14,
"fill" : 10,
"inv" : 8,
"lgcp" : 4,
"mux2" : 6,
"mux4" : 6,
"nand2" : 2,
"nand2b" : 2,
"nand3" : 2,
"nand3b" : 2,
"nand4" : 2,
"nor2" : 3,
"nor2b" : 3,
"nor3" : 3,
"nor4" : 3,
"o21ai" : 13,
"or2" : 1,
"or3" : 1,
"or4" : 1,
"sdfbbp" : 5,
"sighold" : 14,
"slgcp" : 4,
"tiehi" : 14,
"tielo" : 14,
"xnor2" : 3,
"xor2" : 1
}
}
ihp/cells.json
+232
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{
"a21o" : {
"description" : "2-input AND into first input of 2-input OR.",
"doc_name": "AO21x",
"doc_ref" : 7
},
"a21oi" : {
"description" : "2-input AND into first input of 2-input NOR.",
"doc_name": "A21OIx",
"doc_ref" : 1
},
"a221oi" : {
"description" : "2-input AND into first two inputs of 3-input NOR.",
"doc_name": "A221OI",
"doc_ref" : 2
},
"a22oi" : {
"description" : "2-input AND into both inputs of 2-input NOR.",
"doc_name": "A22OI",
"doc_ref" : 3
},
"and2" : {
"description" : "2-input AND.",
"doc_name": "AND2x",
"doc_ref" : 4
},
"and3" : {
"description" : "3-input AND.",
"doc_name": "AND3x",
"doc_ref" : 5
},
"and4" : {
"description" : "4-input AND.",
"doc_name": "AND4x",
"doc_ref" : 6
},
"antennanp" : {
"description" : "Antenna tie-down diode.",
"doc_name": "NP_ANT",
"doc_ref" : 38
},
"buf" : {
"description" : "Buffer.",
"doc_name": "BUx",
"doc_ref" : 9
},
"decap" : {
"description" : "Decoupling capacitance filler.",
"doc_name": "DECAPx",
"doc_ref" : 10
},
"dfrbp" : {
"description" : "Delay flop, inverted reset, complementary outputs.",
"doc_name": "DFFRRx",
"doc_ref" : 11
},
"dlhq" : {
"description" : "Delay latch, non-inverted enable, single output.",
"doc_name": "DLHQ",
"doc_ref" : 12
},
"dlhr" : {
"description" : "Delay latch, inverted reset, non-inverted enable, complementary outputs.",
"doc_name": "DLHR",
"doc_ref" : 14
},
"dlhrq" : {
"description" : "Delay latch, inverted reset, non-inverted enable, single output.",
"doc_name": "DLHRQ",
"doc_ref" : 13
},
"dllr" : {
"description" : "Delay latch, inverted reset, inverted enable, complementary outputs.",
"doc_name": "DLLR",
"doc_ref" : 16
},
"dllrq" : {
"description" : "Delay latch, inverted reset, inverted enable, single output.",
"doc_name": "DLLRQ",
"doc_ref" : 15
},
"dlygate4sd1" : {
"description" : "Delay Buffer 4-stage ... length inner stage gates.",
"doc_name": "DLY1",
"doc_ref" : 17
},
"dlygate4sd2" : {
"description" : "Delay Buffer 4-stage ... length inner stage gates.",
"doc_name": "DLY2",
"doc_ref" : 18
},
"dlygate4sd3" : {
"description" : "Delay Buffer 4-stage ... length inner stage gates.",
"doc_name": "DLY4",
"doc_ref" : 19
},
"ebufn" : {
"description" : "Tri-state buffer, negative enable.",
"doc_name": "BTLx",
"doc_ref" : 8
},
"einvn" : {
"description" : "Tri-state inverter, negative enable.",
"doc_name": "EINVINx, ITL",
"doc_ref" : 20
},
"fill" : {
"description" : "Fill cell.",
"doc_name": "FILLx",
"doc_ref" : 21
},
"inv" : {
"description" : "Inverter.",
"doc_name": "INx",
"doc_ref" : 23
},
"lgcp" : {
"description" : "Clock gate.",
"doc_name": "GCLK",
"doc_ref" : 22
},
"mux2" : {
"description" : "2-input multiplexer.",
"doc_name": "MUX2x",
"doc_ref" : 26
},
"mux4" : {
"description" : "4-input multiplexer.",
"doc_name": "MUX4",
"doc_ref" : 27
},
"nand2" : {
"description" : "2-input NAND.",
"doc_name": "NAND2x",
"doc_ref" : 30
},
"nand2b" : {
"description" : "2-input NAND, first input inverted.",
"doc_name": "NAND2B1, NAND2B2",
"doc_ref" : 28
},
"nand3" : {
"description" : "3-input NAND.",
"doc_name": "NAND3",
"doc_ref" : 32
},
"nand3b" : {
"description" : "3-input NAND, first input inverted.",
"doc_name": "NAND3B1",
"doc_ref" : 31
},
"nand4" : {
"description" : "4-input NAND.",
"doc_name": "NAND4",
"doc_ref" : 33
},
"nor2" : {
"description" : "2-input NOR.",
"doc_name": "NOR2x",
"doc_ref" : 35
},
"nor2b" : {
"description" : "2-input NOR, first input inverted.",
"doc_name": "NOR2Bx",
"doc_ref" : 34
},
"nor3" : {
"description" : "3-input NOR.",
"doc_name": "NOR3x",
"doc_ref" : 36
},
"nor4" : {
"description" : "4-input NOR.",
"doc_name": "NOR4x",
"doc_ref" : 37
},
"o21ai" : {
"description" : "2-input OR into first input of 2-input NAND.",
"doc_name": "O21AI",
"doc_ref" : 39
},
"or2" : {
"description" : "2-input OR.",
"doc_name": "OR2x",
"doc_ref" : 40
},
"or3" : {
"description" : "3-input OR.",
"doc_name": "OR3x",
"doc_ref" : 41
},
"or4" : {
"description" : "4-input OR.",
"doc_name": "OR4x",
"doc_ref" : 42
},
"sdfbbp" : {
"description" : "Scan delay flop, inverted set, inverted reset, non-inverted clock, complementary outputs.",
"doc_name": "SDFRRS",
"doc_ref" : 43
},
"sighold" : {
"description" : "Cross-coupled inverters.",
"doc_name": "KEEPSTATE",
"doc_ref" : 25
},
"slgcp" : {
"description" : "Scan gated clock.",
"doc_name": "SGCLK",
"doc_ref" : 44
},
"tiehi" : {
"description" : "Constant high output.",
"doc_name": "TIE1",
"doc_ref" : 46
},
"tielo" : {
"description" : "Constant low output.",
"doc_name": "TIE0",
"doc_ref" : 45
},
"xnor2" : {
"description" : "2-input exclusive NOR.",
"doc_name": "XNOR2_1",
"doc_ref" : 47
},
"xor2" : {
"description" : "2-input exclusive OR.",
"doc_name": "XOR2_1",
"doc_ref" : 48
}
}
ihp/constraint.sdc
+13
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set clk_name core_clock
set clk_port_name clk
set clk_period 20
set clk_io_pct 0.2
set clk_port [get_ports $clk_port_name]
create_clock -name $clk_name -period $clk_period $clk_port
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
ihp/def/tt_block_1x1.def
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VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 212160 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 430 BY 1 STEP 480 0 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 504 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 504 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 93 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 53 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_1x2.def
+327
View File
@@ -0,0 +1,327 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 212160 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 430 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 430 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 430 BY 1 STEP 480 0 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 504 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 504 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 441 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 93 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 53 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_2x1.def
+285
View File
@@ -0,0 +1,285 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 427200 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 878 BY 1 STEP 480 0 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 1016 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 1016 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 187 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 107 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_2x2.def
+327
View File
@@ -0,0 +1,327 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 427200 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 878 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 878 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 878 BY 1 STEP 480 0 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 1016 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 1016 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 889 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 187 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 107 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_3x1.def
+285
View File
@@ -0,0 +1,285 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 642240 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1326 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 1528 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 1528 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 281 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 160 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_3x2.def
+327
View File
@@ -0,0 +1,327 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 642240 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 1326 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 1326 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 1326 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 1528 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 1528 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1337 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 281 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 160 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_4x1.def
+285
View File
@@ -0,0 +1,285 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 857280 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1774 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 2040 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 2040 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 376 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 214 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_4x2.def
+327
View File
@@ -0,0 +1,327 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 857280 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 1774 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 1774 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 1774 BY 1 STEP 480 0 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 2040 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 2040 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 1785 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 376 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 214 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_6x1.def
+285
View File
@@ -0,0 +1,285 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1287360 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 2670 BY 1 STEP 480 0 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 3064 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 3064 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 564 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_6x2.def
+327
View File
@@ -0,0 +1,327 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1287360 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 2670 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 2670 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 2670 BY 1 STEP 480 0 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 3064 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 3064 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 2681 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 564 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 322 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_8x1.def
+285
View File
@@ -0,0 +1,285 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1717440 154980 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 3566 BY 1 STEP 480 0 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 4088 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 4088 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 368 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 322 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 753 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 67 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 429 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 38 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 154480 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 154480 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 154480 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 154480 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 154480 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 154480 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 154480 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 154480 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 154480 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 154480 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 154480 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 154480 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 154480 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 154480 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 154480 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 154480 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 154480 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 154480 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 154480 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 154480 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 154480 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 154480 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 154480 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 154480 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 154480 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 154480 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 154480 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 154480 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 154480 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 154480 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 154480 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 154480 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 154480 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 154480 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 154480 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 154480 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 154480 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 154480 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 154480 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 154480 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 154480 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 154480 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 154480 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/def/tt_block_8x2.def
+327
View File
@@ -0,0 +1,327 @@
VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 1717440 313740 ) ;
ROW ROW_0 CoreSite 2880 3780 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_1 CoreSite 2880 7560 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_2 CoreSite 2880 11340 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_3 CoreSite 2880 15120 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_4 CoreSite 2880 18900 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_5 CoreSite 2880 22680 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_6 CoreSite 2880 26460 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_7 CoreSite 2880 30240 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_8 CoreSite 2880 34020 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_9 CoreSite 2880 37800 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_10 CoreSite 2880 41580 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_11 CoreSite 2880 45360 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_12 CoreSite 2880 49140 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_13 CoreSite 2880 52920 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_14 CoreSite 2880 56700 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_15 CoreSite 2880 60480 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_16 CoreSite 2880 64260 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_17 CoreSite 2880 68040 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_18 CoreSite 2880 71820 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_19 CoreSite 2880 75600 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_20 CoreSite 2880 79380 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_21 CoreSite 2880 83160 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_22 CoreSite 2880 86940 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_23 CoreSite 2880 90720 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_24 CoreSite 2880 94500 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_25 CoreSite 2880 98280 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_26 CoreSite 2880 102060 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_27 CoreSite 2880 105840 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_28 CoreSite 2880 109620 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_29 CoreSite 2880 113400 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_30 CoreSite 2880 117180 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_31 CoreSite 2880 120960 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_32 CoreSite 2880 124740 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_33 CoreSite 2880 128520 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_34 CoreSite 2880 132300 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_35 CoreSite 2880 136080 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_36 CoreSite 2880 139860 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_37 CoreSite 2880 143640 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_38 CoreSite 2880 147420 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_39 CoreSite 2880 151200 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_40 CoreSite 2880 154980 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_41 CoreSite 2880 158760 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_42 CoreSite 2880 162540 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_43 CoreSite 2880 166320 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_44 CoreSite 2880 170100 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_45 CoreSite 2880 173880 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_46 CoreSite 2880 177660 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_47 CoreSite 2880 181440 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_48 CoreSite 2880 185220 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_49 CoreSite 2880 189000 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_50 CoreSite 2880 192780 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_51 CoreSite 2880 196560 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_52 CoreSite 2880 200340 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_53 CoreSite 2880 204120 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_54 CoreSite 2880 207900 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_55 CoreSite 2880 211680 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_56 CoreSite 2880 215460 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_57 CoreSite 2880 219240 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_58 CoreSite 2880 223020 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_59 CoreSite 2880 226800 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_60 CoreSite 2880 230580 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_61 CoreSite 2880 234360 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_62 CoreSite 2880 238140 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_63 CoreSite 2880 241920 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_64 CoreSite 2880 245700 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_65 CoreSite 2880 249480 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_66 CoreSite 2880 253260 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_67 CoreSite 2880 257040 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_68 CoreSite 2880 260820 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_69 CoreSite 2880 264600 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_70 CoreSite 2880 268380 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_71 CoreSite 2880 272160 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_72 CoreSite 2880 275940 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_73 CoreSite 2880 279720 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_74 CoreSite 2880 283500 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_75 CoreSite 2880 287280 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_76 CoreSite 2880 291060 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_77 CoreSite 2880 294840 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_78 CoreSite 2880 298620 N DO 3566 BY 1 STEP 480 0 ;
ROW ROW_79 CoreSite 2880 302400 FS DO 3566 BY 1 STEP 480 0 ;
ROW ROW_80 CoreSite 2880 306180 N DO 3566 BY 1 STEP 480 0 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal1 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal1 ;
TRACKS X 420 DO 4088 STEP 420 LAYER Metal2 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal2 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal3 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal3 ;
TRACKS X 420 DO 4088 STEP 420 LAYER Metal4 ;
TRACKS Y 420 DO 746 STEP 420 LAYER Metal4 ;
TRACKS X 480 DO 3577 STEP 480 LAYER Metal5 ;
TRACKS Y 480 DO 653 STEP 480 LAYER Metal5 ;
TRACKS X 1460 DO 753 STEP 2280 LAYER TopMetal1 ;
TRACKS Y 1460 DO 137 STEP 2280 LAYER TopMetal1 ;
TRACKS X 2000 DO 429 STEP 4000 LAYER TopMetal2 ;
TRACKS Y 2000 DO 78 STEP 4000 LAYER TopMetal2 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 198720 313240 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 202560 313240 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 194880 313240 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 191040 313240 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 187200 313240 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 183360 313240 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 179520 313240 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 175680 313240 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 171840 313240 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 168000 313240 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 164160 313240 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 160320 313240 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 156480 313240 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 152640 313240 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 148800 313240 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 144960 313240 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141120 313240 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 137280 313240 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 133440 313240 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 68160 313240 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 64320 313240 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 60480 313240 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 56640 313240 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52800 313240 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 48960 313240 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 45120 313240 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41280 313240 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 98880 313240 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 95040 313240 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91200 313240 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 87360 313240 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83520 313240 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 79680 313240 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 75840 313240 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72000 313240 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 129600 313240 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 125760 313240 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121920 313240 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 118080 313240 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 114240 313240 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110400 313240 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 106560 313240 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER Metal5 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102720 313240 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
ihp/pdn.tcl
+18
View File
@@ -0,0 +1,18 @@
# global connections
add_global_connection -net {VDD} -pin_pattern {^VDD$} -power
add_global_connection -net {VDD} -pin_pattern {^VDDPE$}
add_global_connection -net {VDD} -pin_pattern {^VDDCE$}
add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground
add_global_connection -net {VSS} -pin_pattern {^VSSE$}
global_connect
# voltage domains
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
# standard cell grid
define_pdn_grid -name {grid} -voltage_domains {CORE}
add_pdn_stripe -grid {grid} -layer {Metal1} -width {0.44} -pitch {7.56} -offset {0} -extend_to_boundary -followpins
add_pdn_stripe -grid {grid} -layer {Metal5} -width {2.200} -pitch {75.6} -offset {13.600} -extend_to_boundary
add_pdn_stripe -grid {grid} -layer {TopMetal1} -width {1.800} -pitch {75.6} -offset {13.570} -extend_to_boundary
add_pdn_connect -grid {grid} -layers {Metal1 Metal5}
add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1}
ihp/tile_sizes.yaml
+12
View File
@@ -0,0 +1,12 @@
1x1: "0 0 212.16 154.98"
1x2: "0 0 212.16 313.74"
2x1: "0 0 427.20 154.98"
2x2: "0 0 427.20 313.74"
3x1: "0 0 642.24 154.98"
3x2: "0 0 642.24 313.74"
4x1: "0 0 857.28 154.98"
4x2: "0 0 857.28 313.74"
6x1: "0 0 1287.36 154.98"
6x2: "0 0 1287.36 313.74"
8x1: "0 0 1717.44 154.98"
8x2: "0 0 1717.44 313.74"