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fix(precheck): disable power pin check for IHP

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IHP provided verilog models do not have power ports, so we don't use powered netlists, and thus no need to check for power pins in the GL verilog.
This commit is contained in:
Uri Shaked
2025-04-16 17:12:34 +03:00
parent 746789020e
commit fe543406d6
1 changed files with 1 additions and 0 deletions
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precheck/precheck.py
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@@ -370,6 +370,7 @@ def main():
{ {
"name": "Power pin check", "name": "Power pin check",
"check": lambda: power_pin_check(verilog_file, lef_file, uses_3v3), "check": lambda: power_pin_check(verilog_file, lef_file, uses_3v3),
"tech": "sky130",
}, },
{"name": "Layer check", "check": lambda: layer_check(gds_file, tech)}, {"name": "Layer check", "check": lambda: layer_check(gds_file, tech)},
{"name": "Cell name check", "check": lambda: cell_name_check(gds_file)}, {"name": "Cell name check", "check": lambda: cell_name_check(gds_file)},