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138 Commits
Author SHA1 Message Date
Uri Shaked 6924b7464b fix: hardening fails with openlane v2024.05.28 
/bin/bash is no longer present in the container image, so we had to remove it from the docker command line
 2024-06-02 10:22:53 +03:00
Uri Shaked c7cd708524 fix: remove support for openlane yaml config 
see https://github.com/TinyTapeout/tt-support-tools/pull/55#issuecomment-2138626540 for reasoning
 2024-06-01 17:25:23 +03:00
htfabandhtfab 59c9f8e2db feat: add support for json config files (#55) 
* feat: add support for json config files

* feat: make json the preferred config format

* feat: allow yaml config format

* feat!: remove compatibility tweaks for tt07's config.tcl

---------

Co-authored-by: htfab <mpw@htamas.net>
 2024-06-01 17:23:33 +03:00
Uri Shaked 11b2d371b4 fix(documentation): exit with error code if PDF generation fails 2024-05-29 17:02:39 +03:00
htfab 2b48c36ecb fix: remove progress bar in github actions 
It breaks the log as every refresh is shown as a new line.
 2024-05-17 20:51:32 +03:00
htfab a791fde25c feat: allow hardening with openlane2 2024-05-16 23:34:05 +03:00
matt venn d8d3836cf8 Update project.py 
fix 'how to use' error message
 2024-05-14 15:15:53 +02:00
htfab c36f3a3615 feat(datasheet): add analog pins to project pdf 2024-05-07 08:47:00 +03:00
htfab b3321a93c6 feat(datasheet): add analog pins to Project class 2024-05-07 08:47:00 +03:00
htfab 8ddef688df feat(datasheet): use mustache for project_preview 2024-05-07 08:47:00 +03:00
Uri Shaked 0c171af9b4 feat(fpga): read seed / target frequency from environment 
Read the values from TT_FPGA_SEED / TT_FPGA_FREQ, and default to 12 MHz frequency.
 2024-05-01 23:47:35 +03:00
Uri Shaked b6ec741349 feat(fpga): initial implementation 
Adds a new `tt_tool.py --create-fpga-bitstream` flag that creates a TT Sim FPGA bitstream from the user's project.
 2024-05-01 23:13:21 +03:00
Uri Shaked 60c8ff8b8e fix(configure): update synth stats paths for tt06 2024-04-26 12:23:38 +03:00
htfab bc500a3a56 fix(docs): remove text labels from subcells in png 2024-04-17 14:29:49 +03:00
Uri Shaked d5153c3f22 fix(tt_tool): clock issue warnings break with custom openlane configs 
they break when some of the steps are disabled, e.g. https://github.com/iic-jku/jku-tt06-tdc-v2/
 2024-04-13 20:31:27 +02:00
Uri Shaked 9c7ebcb731 feat(tt_tool): display clock issue warnings #34 2024-04-08 15:10:47 +03:00
Uri Shaked 16fb26f5e6 fix(datasheet): images missing #32 2024-04-08 15:04:28 +03:00
Uri Shaked 1ebe1ef29b fix(configure): correct project type in shuttle_index.md for analog projects 
was "HDL", should be "Analog"
 2024-04-06 14:51:48 +03:00
Uri Shaked ca190609c6 fix: pass yosys commands through an environment variable 
should be safer than passing them on shell commandline
 2024-03-30 01:32:08 +03:00
Uri Shaked 1e052887a2 fix: yowasp-yosys chokes on complex verilog modules 
reproduces with https://github.com/Lucaz97/tt06_RNG2

as a workaround, we first try to read the first verilog source file, and only if we can't find the top level verilog module there, we read the rest of the files.
 2024-03-30 01:12:06 +03:00
Uri Shaked b1a2a3bb98 feat(configure): initial support for analog module placement 2024-03-16 23:26:56 +02:00
Uri Shaked 51bb1d0bf5 fix: don't generate pg_vdd property in tt-multiplexer's modules.yaml 
All user macros are now power gated by default
 2024-03-13 23:03:07 +02:00
Uri Shaked 12c79b065c fix(tt_tool): broken PNG render for openlane projects 2024-03-01 15:43:45 +02:00
Uri Shaked 49b8e8724c feat(tt_tool): support for specifying custom GDS file for PNG render 
tinytapeout/tt-gds-action#12
 2024-02-29 22:38:35 +02:00
Uri Shaked f6fae279c1 fix: projects that manually instantiate standard cells fail 
remove an assestion that causes these projects to fail

fix #31
 2024-02-21 15:31:28 +02:00
Uri Shaked e8c5040dc5 fix(tt_tool): fails on non-analog projects 2024-02-01 13:06:19 +02:00
Uri Shaked 7126553f3c feat: analog project support 
handle ua[7:0] pins in analog modules
 2024-01-30 21:43:04 +02:00
Uri Shaked 87bc6c0738 fix(configure): running with --update-shuttle fails 
We're looking for the RTL source file instead of the GL files
 2024-01-23 14:23:58 +02:00
Uri Shaked 66e1fc3ff0 feat: update tt_block def files for tt06 
The tile sizes have slightly changed as we plan using the openframe caravel variant, as well as power gating all the projects on the shuttle.
 2023-12-31 23:58:59 +02:00
Uri Shaked 9d802fbe8c fix(tt_tool): fails on Wokwi projects 2023-12-26 15:06:28 +02:00
Uri Shaked 1a154feba2 fix(tt_tool): fails to load info.yaml 
also --check-docs fails
 2023-12-23 22:42:47 +02:00
Uri Shaked 45633298e8 fix(docs): update code to support new info.yaml format 2023-12-23 22:37:55 +02:00
Uri Shaked c2c0d8ffbd refactor: add more types 
include types for the new info.yaml
 2023-12-23 21:27:22 +02:00
Uri Shaked 47644b5d71 fix(configure): port detection breaks because of VPWR/VGND 
also, doc generation is broken
 2023-12-21 00:08:16 +02:00
Uri Shaked 3b25920db0 feat: reject modules with extra ports 
also verify port directions
 2023-11-26 00:12:12 +02:00
Uri Shaked 7be3d03064 feat(docs): support new info.yaml/info.md format 2023-11-21 20:41:20 +02:00
Uri Shaked 2c969114d1 feat(tt_tool): add --print-top-module argument 2023-11-21 00:25:49 +02:00
Uri Shaked 6e13c146fc feat: initial support for new info.yaml format 
1. wokwi_id is now optional
2. remove the "picture" property (it's going away)
 2023-11-20 20:18:44 +02:00
Uri Shaked a31ae37296 feat(docs): update for tt05 (WiP) 2023-11-09 17:00:59 +02:00
Uri Shaked 98e7cb27ac fix: broken tt_tool 
"power_gated" support broke tt_tool
 2023-10-27 20:37:15 +03:00
Uri Shaked 765ae2df56 feat: support for "power_gated" property in commit_id.json 2023-10-27 19:44:47 +03:00
Uri Shaked 300a179400 fix: fails when project is missing synthesis-stats.txt 2023-10-13 12:03:57 +03:00
Uri Shaked 462004f9e0 feat: generate gl includes for user projects 
This enables running GL tests on the final GL netlist of the actual chip
 2023-10-01 23:27:36 +03:00
Uri Shaked aa8f760375 style: fix lint errors + reformat source with black 2023-09-21 22:30:52 +03:00
Uri Shaked 3f8a47659c fix: path to openlane2 yosys synth log 2023-09-21 08:17:15 +03:00
Uri Shaked 3b469b9488 refactor: add types to project.py 2023-09-19 19:52:47 +03:00
Anton MaurovicandAnton Maurovic 76835903c0 peftGDS=>PNG render improvement for GitHub Actions and local (#28) 
* Add --create-png-preview option; more-robust GDS to PNG rendering for GHA

* Minor update to --create-png-preview

* Change --create-png-preview to just be a --create-png replacement

* Minor --create-png improvement

---------

Co-authored-by: Anton Maurovic <algo@foogle.com>
 2023-09-19 07:27:59 +03:00
Uri Shaked b02cc19e78 fix: shuttle config fails as tt_um_chip_rom verilog is missing 
The Chip ROM is now auto generated, so the GL verilog only exists after we configure the shuttle
 2023-09-10 20:23:48 +03:00
Uri Shaked cc1b5806b2 fix: correct project gl path when running configure.py 2023-09-09 21:39:08 +03:00
Boundary Effect 8717325500 feat(datasheet): allow pdf images 2023-09-09 00:11:51 +02:00