100 Commits
Author SHA1 Message Date
Uri Shaked 3e79f13afa fix: bump klayout version to 0.29.12
0.29.10 was yanked out of pip, breaking the build
2025-08-08 20:43:27 +03:00
Uri Shaked 2172f22287 fix(rom): fails to build on CF shuttles
Add "s", "k", "y" to the 7-segment encoding dictionary
2025-06-17 12:50:28 +03:00
Uri Shaked 869892b7ff fix(logo): support to longer shuttle names (e.g. TTCAD25a) 2025-05-26 19:35:31 +03:00
Uri Shaked a5f34e351f fix(rom): fails to build on cadence shuttles
Add "c", "a", "d" to the 7-segment encoding dictionary.
2025-05-26 19:30:36 +03:00
Uri Shaked 0985eb1d46 feat(rom): support for reading sequentially
This helps in case where some of the `ui_in` pins can't be set due to a plugged-in Pmod or other conflicting driver.
2025-02-02 11:13:48 +02:00
Uri Shaked 8f2ff888d6 style(rom): format verilog code with verible 2025-02-02 10:48:37 +02:00
Uri Shaked a48b1c7446 feat(configure): support for brotli-compressed GDS files
Recently, we started compressing GDS files larger than 25 MB due to GitHub REST API blob size limitations.
2024-11-05 14:56:53 +02:00
Uri Shaked b176ed7ced feat(orfs): allow overriding PDN config 2024-10-25 10:02:14 +03:00
Uri Shaked 05f4c62dc1 feat(configure): add no_power_gating configuration
When set, it configures all user projects with `pg_vdd: false`. This is for ihp0p2 shuttle, which doesn't have power gating yet (tt-multiplexer defaults to enable the pg when `pg_vdd` is not explicitly specified).
2024-10-22 11:50:26 +03:00
Uri Shaked d1e8e31569 feat(configure): add --create-ihp-submission command
similar to create-efabless-submission, but uses the ihp directory and skips copying user_defines.v
2024-10-21 21:53:54 +03:00
Uri Shaked f3e3861176 fix(shuttle): missing powered GL netlists for IHP
Hardening requires powered netlists, GL required unpowered netlists. So now we keep both.
2024-10-21 16:53:14 +03:00
Uri Shaked 4eb37893cb fix(configure): fails on ihp user submissions
IHP submissions do not have powered netlists, so add a flag to specify that in the shuttles config.yaml file.
2024-10-21 16:01:33 +03:00
Uri Shaked 9dc2af14c8 feat(configure): make top_level_macro configurable
For IHP shuttles, we need "tt_ihp_wrapper" instead of "openframe_project_wrapper"
2024-10-21 13:31:51 +03:00
Uri Shaked cbbf76df98 feat(rom): ihp hardening support 2024-10-21 10:09:05 +03:00
Uri Shaked 474b576b3e fix(rom): fails to build on ihp shuttles
Add "i", "h", "p" to the 7-segment encoding dictionary.
2024-10-20 23:44:55 +03:00
Uri Shaked 07e91d894b chore: upgrade cocotb to 1.9.1 #69
cocotb==1.8.1 fails building on macOS ARM-based systems. More recent versions build successfully.

resolves #69
2024-09-27 12:19:45 +03:00
Uri Shaked 96f3577cad chore(precheck): update klayout DRC deck
following efabless/mpw_precheck#289
2024-09-11 23:39:59 +03:00
Uri Shaked 4b04660726 fix(reharden): support new shuttle index format (v3) 2024-09-09 23:19:15 +03:00
Uri Shaked 587b6cb0d0 fix: type error 2024-08-30 11:44:13 +03:00
Uri Shaked d3ed62bc00 fix(configure): support declaring power ports as inout
OpenLane 2.1.1 produces a verilog netlist with the power ports declared as "inout", where as 2.0.8 and earlier declared the power ports as "input". Change our scripts to accept "inout" as a valid direction for the power ports.
2024-08-30 11:39:52 +03:00
Uri Shaked 3c88e6eb04 cleanup(website): remove hugo related functionality
Project pages are now dynamically generated based on the shuttle index.
2024-07-16 15:15:09 +03:00
Uri Shaked 63eb3d550f feat(configure): copy tt_pg_1v8_4 macro 2024-07-04 22:17:53 +03:00
Uri Shaked 054e41b839 feat(configure): set "pg_vaa" in modules.yaml for 3v3 projects
This property tells the mux to include 3v3 power gate (in addition to the standard 1v8 power gate)
2024-07-04 21:38:40 +03:00
Uri Shaked 3c25ae08a6 feat(analog): magic script to create a new analog project 2024-06-26 21:22:52 +03:00
Uri Shaked 674fdc7ef7 fix(precheck): update analog template paths 2024-06-18 14:29:40 +03:00
Uri Shaked ada2e9215e feat(def): update analog templates for tt08 2024-06-18 14:25:27 +03:00
Uri Shaked e64b30fcb3 feat(def): 3x4, 4x4 and 5x4 tile sizes 2024-06-10 12:14:40 +03:00
Uri Shaked a4a87edf2a feat(configure): copy new tt08 power gate macros
tt_pg_1v8_1, tt_pg_1v8_2, and tt_pg_3v3_2
2024-06-09 16:11:30 +03:00
Uri Shaked 3d87be1a9c feat(def): update tt_block def files for tt08
The pin positions have changed to keep space for the analog supply voltage gating transistor
2024-06-09 08:42:59 +03:00
Uri Shaked 6924b7464b fix: hardening fails with openlane v2024.05.28
/bin/bash is no longer present in the container image, so we had to remove it from the docker command line
2024-06-02 10:22:53 +03:00
Uri Shaked c7cd708524 fix: remove support for openlane yaml config
see https://github.com/TinyTapeout/tt-support-tools/pull/55#issuecomment-2138626540 for reasoning
2024-06-01 17:25:23 +03:00
Uri Shaked 11b2d371b4 fix(documentation): exit with error code if PDF generation fails 2024-05-29 17:02:39 +03:00
Uri Shaked 17e08942b2 feat(rom): add Magic and CRC32 fields 2024-05-29 16:18:08 +03:00
Uri Shaked bcf20bea0b fix(datasheet): broken datasheet
it broke after the fix from 74796c81c7
2024-05-29 15:55:39 +03:00
Uri Shaked 74796c81c7 fix: analog designs always get 6 pins connected
instead, we should read the `analog_pins` setting from the project's info.yaml
2024-05-29 13:19:29 +03:00
Uri Shaked 8e2da84a18 feat: python 3.12 support #53
close #53
2024-05-20 10:36:19 +03:00
Uri Shaked d2d27ab36c fix(precheck): fails on projects in shuttle repository
It can't find info.yaml, since it's looking for it in the parent directory of the gds while info.yaml is in the same directory as the gds.
2024-05-07 09:01:09 +03:00
Uri Shaked 79f41ef2e1 fix(datasheet): shuttle id missing in hugo content index
We generate {shuttle_id} instead of actually putting the shuttle id there, causing the shuttle map not to appear.
2024-05-07 08:47:00 +03:00
Uri Shaked af1f250dba fix(datasheet): broken full gds render / chip map 2024-05-07 00:24:55 +03:00
Uri Shaked 0c171af9b4 feat(fpga): read seed / target frequency from environment
Read the values from TT_FPGA_SEED / TT_FPGA_FREQ, and default to 12 MHz frequency.
2024-05-01 23:47:35 +03:00
Uri Shaked b6ec741349 feat(fpga): initial implementation
Adds a new `tt_tool.py --create-fpga-bitstream` flag that creates a TT Sim FPGA bitstream from the user's project.
2024-05-01 23:13:21 +03:00
Uri Shaked 81bffaf9d6 fix(datasheet): update website index header for TT07 2024-05-01 01:25:21 +03:00
Uri Shaked 51e5747c09 fix(tt_tool): analog project can have up to 6 analog pins 2024-04-27 22:30:43 +03:00
Uri Shaked 60c8ff8b8e fix(configure): update synth stats paths for tt06 2024-04-26 12:23:38 +03:00
Uri Shaked 4b2bb6d000 feat(precheck): verify top level macro name
This issue appeared in tt06, in the following analog project: https://github.com/davidparent/tt_resistor_test/tree/fdc74c92ec0ec2b9817f0ea6823daa62f8ca5401/
2024-04-23 22:57:52 +03:00
Uri Shaked 793d01ab13 feat(tt_tool): improve "pinout" section validation
- Verify that the user filled the pinout (at least one pin description)
- Disallow unrecognized keys
2024-04-23 00:10:44 +03:00
Uri Shaked 730fb02726 fix(website): images missing from website
TinyTapeout/tinytapeout_www#84
2024-04-22 00:12:20 +03:00
Uri Shaked a6d2dae7aa fix(precheck): remove unused --markdown-report arg
the markdown report is always generated anyway
2024-04-21 00:18:35 +03:00
Uri Shaked 3067026096 feat(precheck): add prBoundary check
verifies that prBoundary layer exists
2024-04-21 00:17:48 +03:00
Uri Shaked ef33610c61 feat: update analog templates for tt07
make the analog pins wider - 0.9um instead of 0.6 um
2024-04-20 13:39:53 +03:00
Uri Shaked 1f66d890ef fix(configure): project loading broken 2024-04-20 01:06:04 +03:00
Uri Shaked f8dc00aeac feat(precheck): add zeroarea check 2024-04-20 00:36:09 +03:00
Uri Shaked bd22f82b1b fix(configure): unhappy types 2024-04-20 00:26:49 +03:00
Uri Shaked 7f56a586c0 feat(configure): support for loading only a subset of the projects
specified by the `TT_ONLY_PROJECTS` environment variable, e.g.:

```bash
TT_ONLY_PROJECTS="tt_um_chip_rom,tt_um_factory_test"
```
2024-04-19 17:39:16 +03:00
Uri Shaked c74b14ac00 fix(datasheet): don't escape latex in user docs (info.md) 2024-04-17 21:28:47 +03:00
Uri Shaked eed8309348 chore(precheck): update klayout DRC rules
following efabless/mpw_precheck#271
2024-04-16 22:39:54 +03:00
Uri Shaked d5153c3f22 fix(tt_tool): clock issue warnings break with custom openlane configs
they break when some of the steps are disabled, e.g. https://github.com/iic-jku/jku-tt06-tdc-v2/
2024-04-13 20:31:27 +02:00
Uri Shaked d9a6d6206d fix(datasheet): broken images 2024-04-11 15:14:31 +03:00
Uri Shaked 9c7ebcb731 feat(tt_tool): display clock issue warnings #34 2024-04-08 15:10:47 +03:00
Uri Shaked 16fb26f5e6 fix(datasheet): images missing #32 2024-04-08 15:04:28 +03:00
Uri Shaked 1ebe1ef29b fix(configure): correct project type in shuttle_index.md for analog projects
was "HDL", should be "Analog"
2024-04-06 14:51:48 +03:00
Uri Shaked ef272636b7 ci(test-precheck): update action dependencies 2024-04-05 11:50:00 +03:00
Uri Shaked b544d27db7 fix(precheck): bump klayout dependency
See KLayout/klayout#1670 for details
2024-04-01 21:43:25 +03:00
Uri Shaked 11a1c442ee feat(precheck): pin_label_purposes_overlapping_drawing check 2024-03-31 21:20:37 +03:00
Uri Shaked ca190609c6 fix: pass yosys commands through an environment variable
should be safer than passing them on shell commandline
2024-03-30 01:32:08 +03:00
Uri Shaked 1e052887a2 fix: yowasp-yosys chokes on complex verilog modules
reproduces with https://github.com/Lucaz97/tt06_RNG2

as a workaround, we first try to read the first verilog source file, and only if we can't find the top level verilog module there, we read the rest of the files.
2024-03-30 01:12:06 +03:00
Uri Shaked e3fac0ab40 feat: "layout" section in shuttle_index
contains information about the type each each mux (analog / digital)
2024-03-21 23:36:50 +02:00
Uri Shaked a97e6b03b6 feat(configure): copy analog switch (asw) macro 2024-03-21 18:09:32 +02:00
Uri Shaked 316141d73a fix(ci): mypy check fails
upgrade python from 3.9 to 3.11
2024-03-19 11:47:36 +02:00
Uri Shaked ef5539b7a0 feat: new format for shuttle_index
1. Bump "version" to 3
2. Rename "shuttle" to "name"
2. Rename "mux" to "projects", and turn it from a dict into a list
3. Project entries: add "address" (which was previously the key of the "mux" dict), remove "features" and add optional "analog_pins" with a list of analog pin assignment.
2024-03-18 01:16:22 +02:00
Uri Shaked b1a2a3bb98 feat(configure): initial support for analog module placement 2024-03-16 23:26:56 +02:00
Uri Shaked 8cd1ef73cb ci: upgrade volare action 2024-03-16 23:17:47 +02:00
Uri Shaked 51bb1d0bf5 fix: don't generate pg_vdd property in tt-multiplexer's modules.yaml
All user macros are now power gated by default
2024-03-13 23:03:07 +02:00
Uri Shaked 12c79b065c fix(tt_tool): broken PNG render for openlane projects 2024-03-01 15:43:45 +02:00
Uri Shaked 49b8e8724c feat(tt_tool): support for specifying custom GDS file for PNG render
tinytapeout/tt-gds-action#12
2024-02-29 22:38:35 +02:00
Uri Shaked f6fae279c1 fix: projects that manually instantiate standard cells fail
remove an assestion that causes these projects to fail

fix #31
2024-02-21 15:31:28 +02:00
Uri Shaked e8c5040dc5 fix(tt_tool): fails on non-analog projects 2024-02-01 13:06:19 +02:00
Uri Shaked 7126553f3c feat: analog project support
handle ua[7:0] pins in analog modules
2024-01-30 21:43:04 +02:00
Uri Shaked 65a2a24087 feat: tt_block def file for analog projects
They add eight analog pins (`ua[7:0]`) in addition to the standard Tiny Tapeout digital pins.
2024-01-30 17:28:10 +02:00
Uri Shaked ad9184ec8a chore: remove start_date from config.yaml
we don't use it
2024-01-29 10:41:05 +02:00
Uri Shaked 67529a8120 feat(tt_tool): require that clock_hz be an integer 2024-01-23 14:49:41 +02:00
Uri Shaked 87bc6c0738 fix(configure): running with --update-shuttle fails
We're looking for the RTL source file instead of the GL files
2024-01-23 14:23:58 +02:00
Uri Shaked 66e1fc3ff0 feat: update tt_block def files for tt06
The tile sizes have slightly changed as we plan using the openframe caravel variant, as well as power gating all the projects on the shuttle.
2023-12-31 23:58:59 +02:00
Uri Shaked 9d802fbe8c fix(tt_tool): fails on Wokwi projects 2023-12-26 15:06:28 +02:00
Uri Shaked b45db8f5e1 fix(docs): limit_markdown_headings fails 2023-12-24 00:26:33 +02:00
Uri Shaked 1a154feba2 fix(tt_tool): fails to load info.yaml
also --check-docs fails
2023-12-23 22:42:47 +02:00
Uri Shaked 45633298e8 fix(docs): update code to support new info.yaml format 2023-12-23 22:37:55 +02:00
Uri Shaked c2c0d8ffbd refactor: add more types
include types for the new info.yaml
2023-12-23 21:27:22 +02:00
Uri Shaked 0ea5cec65d feat(docs): rename generated markdown index to shuttle_index.md 2023-12-23 13:04:18 +02:00
Uri Shaked 47644b5d71 fix(configure): port detection breaks because of VPWR/VGND
also, doc generation is broken
2023-12-21 00:08:16 +02:00
Uri Shaked 3b25920db0 feat: reject modules with extra ports
also verify port directions
2023-11-26 00:12:12 +02:00
Uri Shaked c3389a1e87 feat: 6x2 tile size support 2023-11-23 21:28:17 +02:00
Uri Shaked 7be3d03064 feat(docs): support new info.yaml/info.md format 2023-11-21 20:41:20 +02:00
Uri Shaked ed28c2f373 feat(precheck): improve error reporting 2023-11-21 01:30:32 +02:00
Uri Shaked 2c969114d1 feat(tt_tool): add --print-top-module argument 2023-11-21 00:25:49 +02:00
Uri Shaked 6e13c146fc feat: initial support for new info.yaml format
1. wokwi_id is now optional
2. remove the "picture" property (it's going away)
2023-11-20 20:18:44 +02:00
Uri Shaked a97371e83a feat(precheck): make top module name optional
if not given, just assume the top module name is the same at the base name of the given GDS file
2023-11-20 17:06:36 +02:00
Uri Shaked 192baef100 refactor(precheck): add missing types 2023-11-20 15:13:59 +02:00
Uri Shaked 2df21d6e92 feat: precheck (#30)
perform DRC checks on GDS files submitted to Tiny Tapeout
2023-11-20 15:02:41 +02:00
Uri Shaked 6702774d07 feat(rom): update config for latest OpenLane 2
DIE_AREA should be a list of numbers and not a string
2023-11-20 14:57:41 +02:00