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Author SHA1 Message Date
Uri Shaked 3d87be1a9c feat(def): update tt_block def files for tt08 
The pin positions have changed to keep space for the analog supply voltage gating transistor
 2024-06-09 08:42:59 +03:00
Uri Shaked 6924b7464b fix: hardening fails with openlane v2024.05.28 
/bin/bash is no longer present in the container image, so we had to remove it from the docker command line
 2024-06-02 10:22:53 +03:00
Uri Shaked c7cd708524 fix: remove support for openlane yaml config 
see https://github.com/TinyTapeout/tt-support-tools/pull/55#issuecomment-2138626540 for reasoning
 2024-06-01 17:25:23 +03:00
Uri Shaked 11b2d371b4 fix(documentation): exit with error code if PDF generation fails 2024-05-29 17:02:39 +03:00
Uri Shaked 17e08942b2 feat(rom): add Magic and CRC32 fields 2024-05-29 16:18:08 +03:00
Uri Shaked bcf20bea0b fix(datasheet): broken datasheet 
it broke after the fix from 74796c81c7
 2024-05-29 15:55:39 +03:00
Uri Shaked 74796c81c7 fix: analog designs always get 6 pins connected 
instead, we should read the `analog_pins` setting from the project's info.yaml
 2024-05-29 13:19:29 +03:00
Uri Shaked 8e2da84a18 feat: python 3.12 support #53 
close #53
 2024-05-20 10:36:19 +03:00
Uri Shaked d2d27ab36c fix(precheck): fails on projects in shuttle repository 
It can't find info.yaml, since it's looking for it in the parent directory of the gds while info.yaml is in the same directory as the gds.
 2024-05-07 09:01:09 +03:00
Uri Shaked 79f41ef2e1 fix(datasheet): shuttle id missing in hugo content index 
We generate {shuttle_id} instead of actually putting the shuttle id there, causing the shuttle map not to appear.
 2024-05-07 08:47:00 +03:00
Uri Shaked af1f250dba fix(datasheet): broken full gds render / chip map 2024-05-07 00:24:55 +03:00
Uri Shaked 0c171af9b4 feat(fpga): read seed / target frequency from environment 
Read the values from TT_FPGA_SEED / TT_FPGA_FREQ, and default to 12 MHz frequency.
 2024-05-01 23:47:35 +03:00
Uri Shaked b6ec741349 feat(fpga): initial implementation 
Adds a new `tt_tool.py --create-fpga-bitstream` flag that creates a TT Sim FPGA bitstream from the user's project.
 2024-05-01 23:13:21 +03:00
Uri Shaked 81bffaf9d6 fix(datasheet): update website index header for TT07 2024-05-01 01:25:21 +03:00
Uri Shaked 51e5747c09 fix(tt_tool): analog project can have up to 6 analog pins 2024-04-27 22:30:43 +03:00
Uri Shaked 60c8ff8b8e fix(configure): update synth stats paths for tt06 2024-04-26 12:23:38 +03:00
Uri Shaked 4b2bb6d000 feat(precheck): verify top level macro name 
This issue appeared in tt06, in the following analog project: https://github.com/davidparent/tt_resistor_test/tree/fdc74c92ec0ec2b9817f0ea6823daa62f8ca5401/
 2024-04-23 22:57:52 +03:00
Uri Shaked 793d01ab13 feat(tt_tool): improve "pinout" section validation 
- Verify that the user filled the pinout (at least one pin description)
- Disallow unrecognized keys
 2024-04-23 00:10:44 +03:00
Uri Shaked 730fb02726 fix(website): images missing from website 
TinyTapeout/tinytapeout_www#84
 2024-04-22 00:12:20 +03:00
Uri Shaked a6d2dae7aa fix(precheck): remove unused --markdown-report arg 
the markdown report is always generated anyway
 2024-04-21 00:18:35 +03:00
Uri Shaked 3067026096 feat(precheck): add prBoundary check 
verifies that prBoundary layer exists
 2024-04-21 00:17:48 +03:00
Uri Shaked ef33610c61 feat: update analog templates for tt07 
make the analog pins wider - 0.9um instead of 0.6 um
 2024-04-20 13:39:53 +03:00
Uri Shaked 1f66d890ef fix(configure): project loading broken 2024-04-20 01:06:04 +03:00
Uri Shaked f8dc00aeac feat(precheck): add zeroarea check 2024-04-20 00:36:09 +03:00
Uri Shaked bd22f82b1b fix(configure): unhappy types 2024-04-20 00:26:49 +03:00
Uri Shaked 7f56a586c0 feat(configure): support for loading only a subset of the projects 
specified by the `TT_ONLY_PROJECTS` environment variable, e.g.:

```bash
TT_ONLY_PROJECTS="tt_um_chip_rom,tt_um_factory_test"
```
 2024-04-19 17:39:16 +03:00
Uri Shaked c74b14ac00 fix(datasheet): don't escape latex in user docs (info.md) 2024-04-17 21:28:47 +03:00
Uri Shaked eed8309348 chore(precheck): update klayout DRC rules 
following efabless/mpw_precheck#271
 2024-04-16 22:39:54 +03:00
Uri Shaked d5153c3f22 fix(tt_tool): clock issue warnings break with custom openlane configs 
they break when some of the steps are disabled, e.g. https://github.com/iic-jku/jku-tt06-tdc-v2/
 2024-04-13 20:31:27 +02:00
Uri Shaked d9a6d6206d fix(datasheet): broken images 2024-04-11 15:14:31 +03:00
Uri Shaked 9c7ebcb731 feat(tt_tool): display clock issue warnings #34 2024-04-08 15:10:47 +03:00
Uri Shaked 16fb26f5e6 fix(datasheet): images missing #32 2024-04-08 15:04:28 +03:00
Uri Shaked 1ebe1ef29b fix(configure): correct project type in shuttle_index.md for analog projects 
was "HDL", should be "Analog"
 2024-04-06 14:51:48 +03:00
Uri Shaked ef272636b7 ci(test-precheck): update action dependencies 2024-04-05 11:50:00 +03:00
Uri Shaked b544d27db7 fix(precheck): bump klayout dependency 
See KLayout/klayout#1670 for details
 2024-04-01 21:43:25 +03:00
Uri Shaked 11a1c442ee feat(precheck): pin_label_purposes_overlapping_drawing check 2024-03-31 21:20:37 +03:00
Uri Shaked ca190609c6 fix: pass yosys commands through an environment variable 
should be safer than passing them on shell commandline
 2024-03-30 01:32:08 +03:00
Uri Shaked 1e052887a2 fix: yowasp-yosys chokes on complex verilog modules 
reproduces with https://github.com/Lucaz97/tt06_RNG2

as a workaround, we first try to read the first verilog source file, and only if we can't find the top level verilog module there, we read the rest of the files.
 2024-03-30 01:12:06 +03:00
Uri Shaked e3fac0ab40 feat: "layout" section in shuttle_index 
contains information about the type each each mux (analog / digital)
 2024-03-21 23:36:50 +02:00
Uri Shaked a97e6b03b6 feat(configure): copy analog switch (asw) macro 2024-03-21 18:09:32 +02:00
Uri Shaked 316141d73a fix(ci): mypy check fails 
upgrade python from 3.9 to 3.11
 2024-03-19 11:47:36 +02:00
Uri Shaked ef5539b7a0 feat: new format for shuttle_index 
1. Bump "version" to 3
2. Rename "shuttle" to "name"
2. Rename "mux" to "projects", and turn it from a dict into a list
3. Project entries: add "address" (which was previously the key of the "mux" dict), remove "features" and add optional "analog_pins" with a list of analog pin assignment.
 2024-03-18 01:16:22 +02:00
Uri Shaked b1a2a3bb98 feat(configure): initial support for analog module placement 2024-03-16 23:26:56 +02:00
Uri Shaked 8cd1ef73cb ci: upgrade volare action 2024-03-16 23:17:47 +02:00
Uri Shaked 51bb1d0bf5 fix: don't generate pg_vdd property in tt-multiplexer's modules.yaml 
All user macros are now power gated by default
 2024-03-13 23:03:07 +02:00
Uri Shaked 12c79b065c fix(tt_tool): broken PNG render for openlane projects 2024-03-01 15:43:45 +02:00
Uri Shaked 49b8e8724c feat(tt_tool): support for specifying custom GDS file for PNG render 
tinytapeout/tt-gds-action#12
 2024-02-29 22:38:35 +02:00
Uri Shaked f6fae279c1 fix: projects that manually instantiate standard cells fail 
remove an assestion that causes these projects to fail

fix #31
 2024-02-21 15:31:28 +02:00
Uri Shaked e8c5040dc5 fix(tt_tool): fails on non-analog projects 2024-02-01 13:06:19 +02:00
Uri Shaked 7126553f3c feat: analog project support 
handle ua[7:0] pins in analog modules
 2024-01-30 21:43:04 +02:00
Uri Shaked 65a2a24087 feat: tt_block def file for analog projects 
They add eight analog pins (`ua[7:0]`) in addition to the standard Tiny Tapeout digital pins.
 2024-01-30 17:28:10 +02:00
Uri Shaked ad9184ec8a chore: remove start_date from config.yaml 
we don't use it
 2024-01-29 10:41:05 +02:00
Uri Shaked 67529a8120 feat(tt_tool): require that clock_hz be an integer 2024-01-23 14:49:41 +02:00
Uri Shaked 87bc6c0738 fix(configure): running with --update-shuttle fails 
We're looking for the RTL source file instead of the GL files
 2024-01-23 14:23:58 +02:00
Uri Shaked 66e1fc3ff0 feat: update tt_block def files for tt06 
The tile sizes have slightly changed as we plan using the openframe caravel variant, as well as power gating all the projects on the shuttle.
 2023-12-31 23:58:59 +02:00
Uri Shaked 9d802fbe8c fix(tt_tool): fails on Wokwi projects 2023-12-26 15:06:28 +02:00
Uri Shaked b45db8f5e1 fix(docs): limit_markdown_headings fails 2023-12-24 00:26:33 +02:00
Uri Shaked 1a154feba2 fix(tt_tool): fails to load info.yaml 
also --check-docs fails
 2023-12-23 22:42:47 +02:00
Uri Shaked 45633298e8 fix(docs): update code to support new info.yaml format 2023-12-23 22:37:55 +02:00
Uri Shaked c2c0d8ffbd refactor: add more types 
include types for the new info.yaml
 2023-12-23 21:27:22 +02:00
Uri Shaked 0ea5cec65d feat(docs): rename generated markdown index to shuttle_index.md 2023-12-23 13:04:18 +02:00
Uri Shaked 47644b5d71 fix(configure): port detection breaks because of VPWR/VGND 
also, doc generation is broken
 2023-12-21 00:08:16 +02:00
Uri Shaked 3b25920db0 feat: reject modules with extra ports 
also verify port directions
 2023-11-26 00:12:12 +02:00
Uri Shaked c3389a1e87 feat: 6x2 tile size support 2023-11-23 21:28:17 +02:00
Uri Shaked 7be3d03064 feat(docs): support new info.yaml/info.md format 2023-11-21 20:41:20 +02:00
Uri Shaked ed28c2f373 feat(precheck): improve error reporting 2023-11-21 01:30:32 +02:00
Uri Shaked 2c969114d1 feat(tt_tool): add --print-top-module argument 2023-11-21 00:25:49 +02:00
Uri Shaked 6e13c146fc feat: initial support for new info.yaml format 
1. wokwi_id is now optional
2. remove the "picture" property (it's going away)
 2023-11-20 20:18:44 +02:00
Uri Shaked a97371e83a feat(precheck): make top module name optional 
if not given, just assume the top module name is the same at the base name of the given GDS file
 2023-11-20 17:06:36 +02:00
Uri Shaked 192baef100 refactor(precheck): add missing types 2023-11-20 15:13:59 +02:00
Uri Shaked 2df21d6e92 feat: precheck (#30) 
perform DRC checks on GDS files submitted to Tiny Tapeout
 2023-11-20 15:02:41 +02:00
Uri Shaked 6702774d07 feat(rom): update config for latest OpenLane 2 
DIE_AREA should be a list of numbers and not a string
 2023-11-20 14:57:41 +02:00
Uri Shaked d551a4cf5a fix(rom): fails if shuttle_id longer than 4 chars 2023-11-20 14:57:41 +02:00
Uri Shaked 17f91aeca2 feat(rom): add "o" and "f" to the segment font 2023-11-20 14:57:41 +02:00
Uri Shaked cbda91be2b feat: preliminary openframe support 2023-11-20 14:57:41 +02:00
Uri Shaked 359dabc326 feat(docs): add chip map 2023-11-11 12:35:14 +02:00
Uri Shaked a31ae37296 feat(docs): update for tt05 (WiP) 2023-11-09 17:00:59 +02:00
Uri Shaked 98e7cb27ac fix: broken tt_tool 
"power_gated" support broke tt_tool
 2023-10-27 20:37:15 +03:00
Uri Shaked 89cd2e77e5 fix: "power_switch" is null in shuttle_index.json 2023-10-27 19:54:54 +03:00
Uri Shaked 765ae2df56 feat: support for "power_gated" property in commit_id.json 2023-10-27 19:44:47 +03:00
Uri Shaked 1822432015 feat(reharden): skip ROM and power gated projects 2023-10-26 22:40:08 +03:00
Uri Shaked c3c940d202 fix(reharden): --clone should also update existing repos 2023-10-26 08:22:35 +03:00
Uri Shaked 7ffd198c55 feat: power gating + split spline mux support 
1. Read mux indices from modules_placed.yaml instead of manually calculating them
2. Add "power_switch" and "analog" fields to shuttle_index.json
3. Copy the power gate macros (tt_pg_vdd_1, tt_pg_vdd_2) into to tt_top directory
 2023-10-21 16:04:52 +03:00
Uri Shaked e6940f63b4 docs(PINOUT): fix broken link 2023-10-20 10:58:07 +03:00
Uri Shaked a221244401 feat: reharden script 2023-10-19 19:57:00 +03:00
Uri Shaked 1c969fe0f3 feat(docs): update README template 
1. Include current shuttle name (instead of hard coded "Tiny Tapeout 03p5")
2. Include the git repo URL / commit hash
 2023-10-17 10:00:30 +03:00
Uri Shaked 300a179400 fix: fails when project is missing synthesis-stats.txt 2023-10-13 12:03:57 +03:00
Uri Shaked 562ebd4f93 feat: update user module def files 
to support tt-multiplexer with power gating. built from tt-multiplexer commit dfbcff452131ea42631f9e358687c22776daffdc
 2023-10-12 22:37:09 +03:00
Uri Shaked 82720e4b84 feat: support for skipping designs 
by specifying ` "skip": true ` in commit_id.json
 2023-10-12 22:34:13 +03:00
Uri Shaked e807454c33 fix: copy powered netlist when building tt_top 
the new power gated tt-multiplexer requires powered netlist for the included macros.
 2023-10-12 19:08:48 +03:00
Uri Shaked 462004f9e0 feat: generate gl includes for user projects 
This enables running GL tests on the final GL netlist of the actual chip
 2023-10-01 23:27:36 +03:00
Uri Shaked 5925525982 fix(datasheet): fails when "bidirectional" is empty 
e.g.

```yaml
documentation:
  ...

# A description of what the inputs do (e.g. red button, SPI CLK, SPI MOSI, etc).
  inputs:
    - sclrn
    - ser
    - rck
    - srck
    - G
# A description of what the outputs do (e.g. status LED, SPI MISO, etc)
  outputs:
    - q[0]
    - q[1]
    - q[2]
    - q[3]
    - q[4]
    - q[5]
    - q[6]
    - q[7]
# A description of what the bidirectional I/O pins do (e.g. I2C SDA, I2C SCL, etc)
  bidirectional:

```
 2023-09-30 07:58:45 +03:00
Uri Shaked 2387160df7 ci: lint job name 2023-09-21 22:31:37 +03:00
Uri Shaked aa8f760375 style: fix lint errors + reformat source with black 2023-09-21 22:30:52 +03:00
Uri Shaked 7d48aab542 ci: add link-check action 2023-09-21 22:25:05 +03:00
Uri Shaked 5725713cbd chore: set up flake8, isort and black with pre-commit 2023-09-21 22:21:59 +03:00
Uri Shaked 3f8a47659c fix: path to openlane2 yosys synth log 2023-09-21 08:17:15 +03:00
Uri Shaked 77fcb0c98f ci: fix broken mypy action 
install required type packages
 2023-09-19 20:55:52 +03:00
Uri Shaked da14cd0502 ci: github action to check python types 2023-09-19 20:44:43 +03:00
Uri Shaked ff0eea8794 refactor: add more types 2023-09-19 20:42:47 +03:00