The previous version of the boundary check was a quick heuristic where
we compared the bounding box of the design to that of the prBoundary layer.
Over time we came across some designs where this is insufficient.
The new check compares the bounding box to the correct project size
based on the .def template and verifies that there is a rectangle of
this exact size in the prBoundary layer at the top level.
The patch also abstracts parsing the .def template into a separate
function since we now use it in two different checks.
Sylvain: The techfile for GF180 is still a bit dodgy in some areas,
especially when reading from GDS and it's rejecting perfectly valid designs.
Wafer.space relies only on KLayout DRC for acceptance so we should do
too for the time being.
The flag enables a second power supply (VAPWR), not necessarily 3.3V (gf180's core is already 3v3), so "uses_3v3" no longer accurately describes its purpose.
Rename it across project_info, precheck, project and shuttle, and update the validation message accordingly.
The legacy "uses_3v3" key is still accepted when reading info.yaml, so existing project configs keep working.
* feat(precheck): check if power pins have `USE` in definition
* fix: expect zero or more spaces, instead of one or more
* feat(precheck): check for missing `USE POWER`
* feat(precheck): check for missing `USE GROUND`
* feat(precheck): add simple README with link to LEF/DEF reference manual
Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.
- no shapes outside project area
- VPWR/VGND present, VAPWR present iff uses_3v3
- no invalid layers
- cell names don't have '#' or '/'
- urpm to nwell spacing satisfies DRC
- analog pins have adjacent metal iff marked as used
* feat(precheck): add support for .gds.br compressed layouts
* fix(precheck): adapt the test suite to changed klayout_checks() signature
---------
Co-authored-by: htfab <mpw@htamas.net>
Flattened sky130 devices in analog layouts can lead to DRC errors.
They are difficult to test for, so as a heuristic we add a warning when magic DRC fails and there are no unflattened sky130 cells.
htfab