* TT FPGA tool, prelim import
* config.ini manager, prelim
* bitstream uploads and FPGA config.ini management
Contributed by @psychogenic, with minor edits by @htfab
This change moves the power rails to TopMetal1, and makes the TopMetal1 layer available for the user designs.
In addition, we now let LibreLane install the PDK instead of having to install it separately.
Each tech has a different metal stackup, so user projects get a different top routing metal layer. tt-support-tools now handles this instead of the user having to worry about this when switching PDKs.
Make the codebase more PDK-agnostic by moving tech-specific code to `tech.py` and tech specific files (e.g. def files, tile_sizes.yaml) to `tech/<pdkname>` subdirectory.