mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 12:46:08 +01:00
Uri Shaked
b6ec741349
Adds a new `tt_tool.py --create-fpga-bitstream` flag that creates a TT Sim FPGA bitstream from the user's project.
38 lines
723 B
Verilog
38 lines
723 B
Verilog
// SPDX-License-Identifier: Apache 2.0
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// Copyright (C) 2024, Tiny Tapeout LTD
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`default_nettype none
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module tt_fpga_top (
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input wire [7:0] ui_in,
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output wire [7:0] uo_out,
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inout wire [7:0] uio,
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input wire clk,
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input wire rst_n
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);
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wire [7:0] uio_in;
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wire [7:0] uio_out;
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wire [7:0] uio_oe;
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SB_IO #(
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.PIN_TYPE(6'b1010_01)
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) uio_pin[7:0] (
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.PACKAGE_PIN(uio),
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.OUTPUT_ENABLE(uio_oe),
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.D_OUT_0(uio_out),
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.D_IN_0(uio_in),
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);
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__tt_um_placeholder user_project (
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.ui_in(ui_in),
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.uo_out(uo_out),
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.uio_in(uio_in),
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.uio_out(uio_out),
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.uio_oe(uio_oe),
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.ena(1'b1),
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.clk(clk),
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.rst_n(rst_n)
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);
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endmodule
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