Files
tt-support-tools/rom/config.json
Uri Shaked cadbfbcd25 feat: Chip ROM auto generation with OpenLane 2
So we can generate the ROM while building the shuttle's GDS
2023-09-10 20:17:58 +03:00

32 lines
852 B
JSON

{
"DESIGN_NAME": "tt_um_chip_rom",
"VERILOG_FILES": "dir::tt_um_chip_rom.v",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 168.36 111.52",
"FP_DEF_TEMPLATE": "ref::$DESIGN_DIR/../def/tt_block_1x1.def",
"FP_IO_HLENGTH": 2,
"FP_IO_VLENGTH": 2,
"//": "use alternative efabless decap cells to solve LI density issue",
"DECAP_CELL": "sky130_fd_sc_hd__decap_3 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_8 sky130_ef_sc_hd__decap_12",
"//": "period is in ns, so 20ns == 50mHz",
"CLOCK_PERIOD": 20,
"CLOCK_PORT": "clk",
"//": "don't use power rings or met5",
"DESIGN_IS_CORE": false,
"RT_MAX_LAYER": "met4",
"//": "save some time",
"RUN_KLAYOUT_XOR": false,
"//": "reduce wasted space",
"TOP_MARGIN_MULT": 1,
"BOTTOM_MARGIN_MULT": 1,
"LEFT_MARGIN_MULT": 6,
"RIGHT_MARGIN_MULT": 6
}