TinyTapeout/tt-support-tools
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tt08
tt-support-tools/def/tt_block_2x2_pg.def
T
Uri Shaked 3d87be1a9c feat(def): update tt_block def files for tt08 
The pin positions have changed to keep space for the analog supply voltage gating transistor
2024-06-09 08:42:59 +03:00

326 lines
14 KiB
Modula-2
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VERSION 5.8 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN tt_um_template ;
UNITS DISTANCE MICRONS 1000 ;
DIEAREA ( 0 0 ) ( 334880 225760 ) ;
ROW ROW_0 unithd 2760 2720 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_1 unithd 2760 5440 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_2 unithd 2760 8160 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_3 unithd 2760 10880 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_4 unithd 2760 13600 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_5 unithd 2760 16320 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_6 unithd 2760 19040 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_7 unithd 2760 21760 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_8 unithd 2760 24480 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_9 unithd 2760 27200 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_10 unithd 2760 29920 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_11 unithd 2760 32640 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_12 unithd 2760 35360 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_13 unithd 2760 38080 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_14 unithd 2760 40800 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_15 unithd 2760 43520 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_16 unithd 2760 46240 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_17 unithd 2760 48960 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_18 unithd 2760 51680 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_19 unithd 2760 54400 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_20 unithd 2760 57120 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_21 unithd 2760 59840 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_22 unithd 2760 62560 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_23 unithd 2760 65280 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_24 unithd 2760 68000 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_25 unithd 2760 70720 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_26 unithd 2760 73440 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_27 unithd 2760 76160 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_28 unithd 2760 78880 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_29 unithd 2760 81600 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_30 unithd 2760 84320 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_31 unithd 2760 87040 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_32 unithd 2760 89760 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_33 unithd 2760 92480 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_34 unithd 2760 95200 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_35 unithd 2760 97920 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_36 unithd 2760 100640 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_37 unithd 2760 103360 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_38 unithd 2760 106080 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_39 unithd 2760 108800 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_40 unithd 2760 111520 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_41 unithd 2760 114240 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_42 unithd 2760 116960 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_43 unithd 2760 119680 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_44 unithd 2760 122400 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_45 unithd 2760 125120 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_46 unithd 2760 127840 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_47 unithd 2760 130560 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_48 unithd 2760 133280 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_49 unithd 2760 136000 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_50 unithd 2760 138720 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_51 unithd 2760 141440 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_52 unithd 2760 144160 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_53 unithd 2760 146880 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_54 unithd 2760 149600 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_55 unithd 2760 152320 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_56 unithd 2760 155040 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_57 unithd 2760 157760 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_58 unithd 2760 160480 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_59 unithd 2760 163200 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_60 unithd 2760 165920 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_61 unithd 2760 168640 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_62 unithd 2760 171360 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_63 unithd 2760 174080 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_64 unithd 2760 176800 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_65 unithd 2760 179520 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_66 unithd 2760 182240 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_67 unithd 2760 184960 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_68 unithd 2760 187680 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_69 unithd 2760 190400 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_70 unithd 2760 193120 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_71 unithd 2760 195840 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_72 unithd 2760 198560 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_73 unithd 2760 201280 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_74 unithd 2760 204000 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_75 unithd 2760 206720 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_76 unithd 2760 209440 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_77 unithd 2760 212160 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_78 unithd 2760 214880 N DO 716 BY 1 STEP 460 0 ;
ROW ROW_79 unithd 2760 217600 FS DO 716 BY 1 STEP 460 0 ;
ROW ROW_80 unithd 2760 220320 N DO 716 BY 1 STEP 460 0 ;
TRACKS X 230 DO 728 STEP 460 LAYER li1 ;
TRACKS Y 170 DO 664 STEP 340 LAYER li1 ;
TRACKS X 170 DO 985 STEP 340 LAYER met1 ;
TRACKS Y 170 DO 664 STEP 340 LAYER met1 ;
TRACKS X 230 DO 728 STEP 460 LAYER met2 ;
TRACKS Y 230 DO 491 STEP 460 LAYER met2 ;
TRACKS X 340 DO 492 STEP 680 LAYER met3 ;
TRACKS Y 340 DO 332 STEP 680 LAYER met3 ;
TRACKS X 460 DO 364 STEP 920 LAYER met4 ;
TRACKS Y 460 DO 245 STEP 920 LAYER met4 ;
TRACKS X 1700 DO 98 STEP 3400 LAYER met5 ;
TRACKS Y 1700 DO 66 STEP 3400 LAYER met5 ;
COMPONENTS 0 ;
END COMPONENTS
PINS 43 ;
- clk + NET clk + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 143980 225260 ) N ;
- ena + NET ena + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 146740 225260 ) N ;
- rst_n + NET rst_n + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 141220 225260 ) N ;
- ui_in[0] + NET ui_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 138460 225260 ) N ;
- ui_in[1] + NET ui_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 135700 225260 ) N ;
- ui_in[2] + NET ui_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 132940 225260 ) N ;
- ui_in[3] + NET ui_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 130180 225260 ) N ;
- ui_in[4] + NET ui_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 127420 225260 ) N ;
- ui_in[5] + NET ui_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 124660 225260 ) N ;
- ui_in[6] + NET ui_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 121900 225260 ) N ;
- ui_in[7] + NET ui_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 119140 225260 ) N ;
- uio_in[0] + NET uio_in[0] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 116380 225260 ) N ;
- uio_in[1] + NET uio_in[1] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 113620 225260 ) N ;
- uio_in[2] + NET uio_in[2] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 110860 225260 ) N ;
- uio_in[3] + NET uio_in[3] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 108100 225260 ) N ;
- uio_in[4] + NET uio_in[4] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 105340 225260 ) N ;
- uio_in[5] + NET uio_in[5] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 102580 225260 ) N ;
- uio_in[6] + NET uio_in[6] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 99820 225260 ) N ;
- uio_in[7] + NET uio_in[7] + DIRECTION INPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 97060 225260 ) N ;
- uio_oe[0] + NET uio_oe[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 50140 225260 ) N ;
- uio_oe[1] + NET uio_oe[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 47380 225260 ) N ;
- uio_oe[2] + NET uio_oe[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 44620 225260 ) N ;
- uio_oe[3] + NET uio_oe[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 41860 225260 ) N ;
- uio_oe[4] + NET uio_oe[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 39100 225260 ) N ;
- uio_oe[5] + NET uio_oe[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 36340 225260 ) N ;
- uio_oe[6] + NET uio_oe[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 33580 225260 ) N ;
- uio_oe[7] + NET uio_oe[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 30820 225260 ) N ;
- uio_out[0] + NET uio_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 72220 225260 ) N ;
- uio_out[1] + NET uio_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 69460 225260 ) N ;
- uio_out[2] + NET uio_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 66700 225260 ) N ;
- uio_out[3] + NET uio_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 63940 225260 ) N ;
- uio_out[4] + NET uio_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 61180 225260 ) N ;
- uio_out[5] + NET uio_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 58420 225260 ) N ;
- uio_out[6] + NET uio_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 55660 225260 ) N ;
- uio_out[7] + NET uio_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 52900 225260 ) N ;
- uo_out[0] + NET uo_out[0] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 94300 225260 ) N ;
- uo_out[1] + NET uo_out[1] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 91540 225260 ) N ;
- uo_out[2] + NET uo_out[2] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 88780 225260 ) N ;
- uo_out[3] + NET uo_out[3] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 86020 225260 ) N ;
- uo_out[4] + NET uo_out[4] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 83260 225260 ) N ;
- uo_out[5] + NET uo_out[5] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 80500 225260 ) N ;
- uo_out[6] + NET uo_out[6] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 77740 225260 ) N ;
- uo_out[7] + NET uo_out[7] + DIRECTION OUTPUT + USE SIGNAL
+ PORT
+ LAYER met4 ( -150 -500 ) ( 150 500 )
+ PLACED ( 74980 225260 ) N ;
END PINS
SPECIALNETS 2 ;
- VGND + USE GROUND ;
- VPWR + USE POWER ;
END SPECIALNETS
NETS 43 ;
- clk ( PIN clk ) + USE SIGNAL ;
- ena ( PIN ena ) + USE SIGNAL ;
- rst_n ( PIN rst_n ) + USE SIGNAL ;
- ui_in[0] ( PIN ui_in[0] ) + USE SIGNAL ;
- ui_in[1] ( PIN ui_in[1] ) + USE SIGNAL ;
- ui_in[2] ( PIN ui_in[2] ) + USE SIGNAL ;
- ui_in[3] ( PIN ui_in[3] ) + USE SIGNAL ;
- ui_in[4] ( PIN ui_in[4] ) + USE SIGNAL ;
- ui_in[5] ( PIN ui_in[5] ) + USE SIGNAL ;
- ui_in[6] ( PIN ui_in[6] ) + USE SIGNAL ;
- ui_in[7] ( PIN ui_in[7] ) + USE SIGNAL ;
- uio_in[0] ( PIN uio_in[0] ) + USE SIGNAL ;
- uio_in[1] ( PIN uio_in[1] ) + USE SIGNAL ;
- uio_in[2] ( PIN uio_in[2] ) + USE SIGNAL ;
- uio_in[3] ( PIN uio_in[3] ) + USE SIGNAL ;
- uio_in[4] ( PIN uio_in[4] ) + USE SIGNAL ;
- uio_in[5] ( PIN uio_in[5] ) + USE SIGNAL ;
- uio_in[6] ( PIN uio_in[6] ) + USE SIGNAL ;
- uio_in[7] ( PIN uio_in[7] ) + USE SIGNAL ;
- uio_oe[0] ( PIN uio_oe[0] ) + USE SIGNAL ;
- uio_oe[1] ( PIN uio_oe[1] ) + USE SIGNAL ;
- uio_oe[2] ( PIN uio_oe[2] ) + USE SIGNAL ;
- uio_oe[3] ( PIN uio_oe[3] ) + USE SIGNAL ;
- uio_oe[4] ( PIN uio_oe[4] ) + USE SIGNAL ;
- uio_oe[5] ( PIN uio_oe[5] ) + USE SIGNAL ;
- uio_oe[6] ( PIN uio_oe[6] ) + USE SIGNAL ;
- uio_oe[7] ( PIN uio_oe[7] ) + USE SIGNAL ;
- uio_out[0] ( PIN uio_out[0] ) + USE SIGNAL ;
- uio_out[1] ( PIN uio_out[1] ) + USE SIGNAL ;
- uio_out[2] ( PIN uio_out[2] ) + USE SIGNAL ;
- uio_out[3] ( PIN uio_out[3] ) + USE SIGNAL ;
- uio_out[4] ( PIN uio_out[4] ) + USE SIGNAL ;
- uio_out[5] ( PIN uio_out[5] ) + USE SIGNAL ;
- uio_out[6] ( PIN uio_out[6] ) + USE SIGNAL ;
- uio_out[7] ( PIN uio_out[7] ) + USE SIGNAL ;
- uo_out[0] ( PIN uo_out[0] ) + USE SIGNAL ;
- uo_out[1] ( PIN uo_out[1] ) + USE SIGNAL ;
- uo_out[2] ( PIN uo_out[2] ) + USE SIGNAL ;
- uo_out[3] ( PIN uo_out[3] ) + USE SIGNAL ;
- uo_out[4] ( PIN uo_out[4] ) + USE SIGNAL ;
- uo_out[5] ( PIN uo_out[5] ) + USE SIGNAL ;
- uo_out[6] ( PIN uo_out[6] ) + USE SIGNAL ;
- uo_out[7] ( PIN uo_out[7] ) + USE SIGNAL ;
END NETS
END DESIGN
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