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39 lines
1.1 KiB
Makefile
39 lines
1.1 KiB
Makefile
# Makefile
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# See https://docs.cocotb.org/en/stable/quickstart.html for more info
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# defaults
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SIM ?= icarus
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TOPLEVEL_LANG ?= verilog
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SRC_DIR = $(PWD)/../src
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# normal simulation
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ifneq ($(GATES),yes)
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# this is the only part you should need to modify:
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VERILOG_SOURCES += $(SRC_DIR)/cells.v $(SRC_DIR)/tt_um_wokwi_WOKWI_ID.v $(PWD)/test_wokwi.v
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else
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# gate level simulation requires some extra setup, you shouldn't need to touch this
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COMPILE_ARGS += -DGL_TEST
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COMPILE_ARGS += -DFUNCTIONAL
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COMPILE_ARGS += -DUSE_POWER_PINS
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COMPILE_ARGS += -DSIM
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COMPILE_ARGS += -DUNIT_DELAY=#1
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VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
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VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
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# this gets copied in by the GDS action workflow
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VERILOG_SOURCES += $(PWD)/test_wokwi.v $(PWD)/gate_level_netlist.v
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endif
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# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
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TOPLEVEL = test_wokwi
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# MODULE is the basename of the Python test file
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MODULE = test
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# include cocotb's make rules to take care of the simulator setup
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include $(shell cocotb-config --makefiles)/Makefile.sim
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