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23 lines
394 B
Verilog
23 lines
394 B
Verilog
// SPDX-License-Identifier: Apache2.0
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`timescale 1ns / 1ps
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`default_nettype none
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module test_wokwi ();
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wire [7:0] uo_out;
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wire [7:0] ui_in;
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tt_um_wokwi_WOKWI_ID dut (
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`ifdef GL_TEST
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.vccd1( 1'b1),
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.vssd1( 1'b0),
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`endif
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.ui_in(ui_in),
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.uo_out(uo_out)
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);
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initial begin
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$dumpfile("wokwi_tb_WOKWI_ID.vcd");
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$dumpvars(0, test_wokwi);
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end
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endmodule
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