tt-support-tools/docs/product/datasheet.yaml

# ---------------------------------------------------------------------------
# Tiny Tapeout product datasheet — all copy, numbers and colours.
#
# Edit this file, then rebuild:
#     python3 docs/product/build.py
#
# Notes for editing:
#   - Every text field is rendered as raw HTML, so <b>, <br> and <a href="...">
#     work anywhere. Write a literal ampersand as &amp;.
#   - Inside a "quoted" value (the table rows), escape any double quote the HTML
#     needs as \" — an unescaped one ends the value and breaks the YAML:
#         "see <a href=\"https://example.com\">the docs</a>"
#     Values written as plain or >- folded text need no escaping.
#   - Table `style` tokens set cell formatting, space separated:
#       name    bold, no wrapping        (first column of most tables)
#       mono    bold + tabular figures   (dimensions, values, signal names)
#       num     tabular figures          (aligned digits)
#       price   bold red + no wrapping   (pricing column)
#       dim     greyed out               (em dashes, secondary text)
#       center  centre aligned
#   - Table rows must have the same number of cells as there are columns.
# ---------------------------------------------------------------------------

doc:
  title: Tiny Tapeout — Datasheet
  wordmark: Tiny Tapeout
  wordmark_sub: ""           # strapline under the wordmark on page 1; blank to hide
  tag: PRODUCT DATASHEET
  ref: ""                    # document reference code; blank to hide on both pages
  page2_title: Electrical Specifications

# Colours and the two page-level type sizes. Everything else scales from these.
theme:
  brand: "#0c66ab"           # header bars and table header rows
  red: "#ec3013"             # accent: labels, rules, prices
  # DATASHEET tag in the header bar. Official Tiny Tapeout brand colours:
  #   yellow #fef244 · cyan #3dfef7 · hot pink #f82381 · pink #fc9f9f · blue #040371
  # Set tag_fg to a dark colour for the light tags, #ffffff for hot pink.
  tag_bg: "#fef244"
  tag_fg: "#040371"
  ink: "#141414"             # body text
  ink_mid: "#55545f"         # secondary text
  ink_faint: "#86858f"       # captions, dashes
  ground: "#f2f1f4"          # zebra stripe on tables
  rule: "#c9c8d0"            # thin rules
  rule_hard: "#141414"       # 2px section rules
  # Chip-layout texture over the header bars, from the tt-datasheet-artwork repo.
  # Blank the filename for flat bars; raise/lower the opacity for more or
  # less texture (0.35 subtle, 0.55 balanced, 0.75 strong).
  bar_texture: bar-texture.png
  bar_texture_opacity: 0.55
  heading_size: 30pt         # page 1 headline
  body_size: 8.3pt           # feature and FAQ body text

assets:
  # Relative to docs/product/assets/. Swap either file and rebuild.
  photo: demoboard.jpg
  font: archivo.woff2

# Supporter logo strip at the foot of page 2. Currently off — uncomment to
# restore it; the logos are still in assets/supporters/. Note it needs about
# 16mm, so page 2 will have to give up spacing elsewhere to fit.
# supporters:
#   heading: Supported by
#   logo_height: 7.5mm
#   items:
#     - {name: ChipFoundry, file: chipfoundry.png}
#     - {name: wafer.space, file: waferspace.png}
#     - {name: Tillitis, file: tillitis.png}
#     - {name: WIT, file: WIT.png, scale: 0.82}
#     - {name: SwissChips, file: swisschips.png, scale: 0.88}
#     - {name: Texplained, file: texplained.jpg}

# --------------------------------------------------------------------------
# PAGE 1
# --------------------------------------------------------------------------

hero:
  eyebrow: Multi project chip · SKY130 / IHP SG13G2 / GF180MCU
  heading: Custom chips from €385
  body: >-
    Tiny Tapeout makes it more accessible than ever to get designs manufactured on a real chip. 
    Submit from a
    GitHub repository and we handle tapeout, packaging, development board and delivery.
  photo_alt: Tiny Tapeout ETR demoboard with a QFN-64 packaged ASIC on a breakout board
  photo_caption: ""          # caption under the hero photo, with a rule above it; blank to hide both

features:
  - kicker: 01 · Toolchain
    title: Local tool install optional
    body: >-
      The whole flow can run in GitHub Actions. Push your repository and your design
      is hardened in the cloud — nothing to install, no licences to buy.
  - kicker: 02 · Languages
    title: HDL agnostic
    body: >-
      Any language that can produce Verilog. Official support for Verilog, 
      community provided templates for VHDL and Chisel.
  - kicker: 03 · I/O
    title: 26 pins, plus analog
    body: >-
      Clock, reset, 8 dedicated inputs, 8 dedicated outputs and 8 bidirectional
      pins — plus up to 6 analog pins where the process allows.
  - kicker: 04 · Process
    title: Three PDKs
    body: >-
      SkyWater SKY130, IHP sg13g2 and GlobalFoundries gf180mcu. Open-source PDKs,
      10+ shuttles per year, no NDAs to sign.
  - kicker: 05 · Hardware
    title: Demoboard available
    body: >-
      An optional RP2350-based demoboard carries the packaged chip and selects
      any project on the die over USB.
  - kicker: 06 · Flexibility
    title: Bring your own flow
    body: >-
      Harden with the supplied open-source LibreLane flow, or use any tools you
      like — commercial or open source — as long as the resulting GDS and LEF
      can be published.

pricing:
  heading: Pricing
  note: ""                   # small grey text right of the heading; blank to hide
  columns:
    - {label: Item, width: "27%", style: name}
    - {label: What it buys you}
    - {label: From, width: "26%", style: price}
  rows:
    - ["1 tile",
       "Roughly 1,000 standard cells of silicon area. Physical dimensions vary by PDK — see page 2.",
       "€70"]
    - ["Analog pin",
       "Multiplexed analog pad access for mixed signal designs. Minimum project size of 2 tiles applies.",
       "€100 <span class=\"t-sub\">/ pin, up to a maximum of 6</span>"]
    - ["Demoboard PCB",
       "Optional add-on: packaged chip on an RP2350 powered demoboard.",
       "€300"]
    - ["Postage &amp; packing",
       "Flat rate worldwide, charged once per demoboard.",
       "€15"]
  footnote: >-
    <b>The €385 headline is one tile (€70) plus a demoboard (€300) plus postage
    (€15)</b> — the smallest order that puts a physical chip in your hand.
    Silicon area and the demoboard are billed separately, so buying area alone
    gets your design manufactured but does not get you a chip. Confirm current
    figures at
    <b><a href="https://app.tinytapeout.com/calculator">app.tinytapeout.com/calculator</a></b>.

faq:
  heading: Frequently asked Questions
  note: FULL FAQ AT TINYTAPEOUT.COM/FAQ
  items:
    - q: How long until I get my chip?
      a: >-
        Fabrication takes 6–9 months, then boards are assembled, tested and
        shipped. Check <a href="https://app.tinytapeout.com/chips">tinytapeout.com/chips</a> for the schedule.
    - q: Do I need chip design experience?
      a: >-
        No. Getting started documentation on the website and help on the Discord community helps beginners get started. 
        Thousands of past projects are public to learn from.
    - q: What do I actually receive?
      a: >-
        Area alone gets your design onto the wafer. Add the demoboard to receive a
        packaged chip, an RP2350 demoboard and a breakout board. Bare chips are not available separately.
    - q: Which processes can I use?
      a: >-
        SkyWater SKY130, IHP sg13g2 and GlobalFoundries gf180mcu, each on its own shuttle schedule.
    - q: Why would I only order area?
      a: >-
        Share the cost of 1 board between a group submitting multiple projects. Save costs by asking us to remotely test your design.
    - q: What are the licence terms?
      a: >-
        Every design must be published publicly under Apache-2.0. The minimum
        submission is GDS + LEF, produced with any toolchain you like. For full terms see <a href="https://tinytapeout.com/terms">tinytapeout.com/terms</a>.

institutions:
  label: Taught and used at
  items:
    - Carnegie Mellon University
    - New York University
    - UC Santa Cruz
    - UC San Diego
    - San Jose State University
    - Oklahoma State University
    - Technical University of Denmark
    - Linköping University
    - Graz University of Technology
    - IEEE
    - SwissChips
    - UK Semiconductor Centre

# --------------------------------------------------------------------------
# PAGE 2
# --------------------------------------------------------------------------

process:
  heading: Process &amp; fabrication
  note: TILE DIMENSIONS PER PDK
  columns:
    - {label: PDK, width: "19%", style: name}
    - {label: Foundry, width: "21%"}
    - {label: Node, width: "20%", style: num}
    - {label: 1×1 tile area, width: "24%", style: mono}
    - {label: Analog support}
  rows:
    - ["SKY130A", "SkyWater", "130 nm", "161.00 × 111.52 µm", "Full"]
    - ["ihp-sg13g2", "IHP", "130 nm BiCMOS", "202.08 × 154.98 µm", "Partial"]
    - ["gf180mcuD", "GlobalFoundries", "180 nm", "346.64 × 160.72 µm", "Partial"]
  footnote: >-
    One tile holds approximately <b>1,000 standard cells</b>. Larger designs are
    built from multi-tile blocks, up to <b>8×4</b> on SKY130A and ihp-sg13g2 and
    up to <b>4×4</b> on gf180mcuD; the sizes available in between differ per PDK.
    Analog projects require a minimum height of 2 tiles.

ratings:
  heading: Absolute maximum ratings
  note: DIGITAL I/O
  columns:
    - {label: Parameter, width: "40%", style: name}
    - {label: Min, width: "13%", style: num}
    - {label: Typ, width: "13%", style: num}
    - {label: Max, width: "13%", style: num}
    - {label: Unit}
  rows:
    - ["I/O supply voltage", "1.71", "3.30", "5.50", "V"]
    - ["Input frequency", "—", "—", "66", "MHz"]
    - ["Output toggle frequency", "—", "—", "33", "MHz"]
    - ["Output drive strength, source/sink", "—", "4", "—", "mA"]
    - ["Demoboard clock generator", "1", "—", "66.5 M", "Hz"]
    - ["Pad-to-tile round-trip latency", "—", "—", "20", "ns"]
    - ["Clock insertion delay, pad to logic", "—", "—", "10", "ns"]
    - ["Pin-to-pin latency variance", "—", "—", "2", "ns"]
  footnote: >-
    Characterised on <b>SKY130A</b> using the <b>sky130_ef_io_gpiov2_pad</b> cell;
    ratings differ per PDK. Inputs are <b>not 5 V tolerant</b> despite the supply
    range. Full per-process figures at
    <b><a href="https://tinytapeout.com/specs/">tinytapeout.com/specs</a></b>.

gpio:
  heading: GPIO pin map
  columns:
    - {label: Signal, width: "34%", style: mono}
    - {label: Width, width: "14%", style: num center}
    - {label: Direction, width: "22%"}
    - {label: Function}
  rows:
    - ["clk", "1", "Input", "Clock"]
    - ["rst_n", "1", "Input", "Reset, active low"]
    - ["ui_in[7:0]", "8", "Input", "General purpose"]
    - ["uo_out[7:0]", "8", "Output", "General purpose"]
    - ["uio[7:0]", "8", "Bidirectional", "Per-pin direction control"]
  linkline: >-
    26 I/O PINS TOTAL ·
    <b><a href="https://tinytapeout.com/specs/gpio/">TINYTAPEOUT.COM/SPECS/GPIO</a></b>

analog:
  heading: Analog I/O
  note: OPTIONAL
  columns:
    - {label: Parameter, style: name}
    - {label: Value, width: "34%", style: mono}
  rows:
    - ["Analog pins, maximum", "6 · ua[0:5]"]
    - ["Series resistance, pad to project", "&lt; 500 Ω"]
    - ["Parasitic capacitance", "&lt; 5 pF"]
    - ["Current per pin, maximum", "4 mA"]
    - ["VDPWR digital supply", "1.8 V"]
    - ["VAPWR analog supply", "3.3 V"]
  linkline: >-
    <b><a href="https://tinytapeout.com/specs/analog/">TINYTAPEOUT.COM/SPECS/ANALOG</a></b>

ordering:
  heading: Ordering information
  note: APP.TINYTAPEOUT.COM/CALCULATOR
  headless: true          # no header row on this table
  columns:
    - {width: "27%", style: name}
    - {}
  rows:
    - ["Shuttle cadence",
       "10+ shuttles per year across the three processes. Check <a href=\"https://app.tinytapeout.com/chips\">tinytapeout.com/chips</a> for the schedule."]
    - ["Lead time",
       "6–9 months in fabrication, then assembly, test and fulfilment."]
    - ["Volume discount",
       "10% off orders over €10,000."]
    - ["Deliverable",
       "Silicon area only for remote or shared test, or area plus the demoboard kit: packaged chip, RP2350 demoboard and breakout board."]
    - ["Design tools",
       "Supplied open-source LibreLane flow running in GitHub Actions, or any commercial or open-source toolchain of your own."]
    - ["Minimum submission",
       "GDS + LEF, produced with any tools, in a public repository under Apache-2.0. Your tools must permit publishing them."]

disclaimer:
  label: Disclaimer
  body: >-
    Specifications are indicative and subject to change between shuttles.
    Electrical characteristics are quoted for the SKY130A process unless stated
    otherwise — consult tinytapeout.com/specs for the process you intend to use.
    Pricing is indicative; confirm current figures with the calculator before
    ordering. Full terms and conditions of sale are published at
    <a href="https://tinytapeout.com/terms">tinytapeout.com/terms</a>.