TinyTapeout/tt-support-tools
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1aab59b59d36783cc349b5cee38a1d02bec2d8e4
tt-support-tools/precheck
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Uri Shaked 1aab59b59d fix(precheck): disable power pin check for IHP 
IHP provided verilog models do not have power ports, so we don't use powered netlists, and thus no need to check for power pins in the GL verilog.
2025-06-27 20:08:03 +03:00
..
reports
feat(precheck): add extra prechecks
2025-01-31 17:53:57 +02:00
tech-files
chore: update efabless -> chipfoundry
2025-06-26 15:09:00 +03:00
.gitignore
feat: precheck (#30)
2023-11-20 15:02:41 +02:00
default.nix
feat: precheck (#30)
2023-11-20 15:02:41 +02:00
klayout_tools.py
feat(precheck): initial IHP support
2025-06-27 20:08:02 +03:00
magic_drc.tcl
feat: precheck (#30)
2023-11-20 15:02:41 +02:00
pin_check.py
feat(precheck): initial IHP support
2025-06-27 20:08:02 +03:00
precheck_failure.py
feat(precheck): add pin checks
2024-05-01 00:55:53 +03:00
precheck.py
fix(precheck): disable power pin check for IHP
2025-06-27 20:08:03 +03:00
pyproject.toml
feat(precheck): add support for .gds.br compressed layouts (#87)
2024-12-12 11:33:38 +02:00
requirements.txt
feat(precheck): add support for .gds.br compressed layouts (#87)
2024-12-12 11:33:38 +02:00
tech_data.py
fix(precheck): update valid list of IHP SG13G2 layers
2025-06-27 20:08:03 +03:00
test_precheck.py
feat(precheck): initial IHP support
2025-06-27 20:08:02 +03:00