mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
1aab59b59d36783cc349b5cee38a1d02bec2d8e4
IHP provided verilog models do not have power ports, so we don't use powered netlists, and thus no need to check for power pins in the GL verilog.
Tiny Tapeout tools
Tools used mostly by the Tiny Tapeout GitHub Actions
Setup
pip install -r requirements.txt
pre-commit install
Documentation
- checks that basic fields are present in the info.yaml
- create a PDF data sheet for this one design
- create SVG and PNG renders of the project's GDS
Reports
- routing & utilisation
- yosys warnings
- standard cell usage and summary
Configuration
- creates a little TCL shim that tells OpenLane where the source is and the name of the top module
- makes sure the top module is not called 'top'
- if you have OpenLane installed locally, then you can harden the design with --harden
Description
Miroir GitHub, requis par le checkout interne de TinyTapeout/tt-gds-action sur Gitea Actions
9 MiB
Languages
Python
95.6%
Tcl
2.9%
Verilog
0.8%
Makefile
0.4%
Nix
0.2%
Other
0.1%