mirror of
https://github.com/TinyTapeout/tt-support-tools.git
synced 2026-11-03 04:36:09 +01:00
Uri Shaked
1de6149a61
Sylvain: The techfile for GF180 is still a bit dodgy in some areas, especially when reading from GDS and it's rejecting perfectly valid designs. Wafer.space relies only on KLayout DRC for acceptance so we should do too for the time being.
558 lines
19 KiB
Python
558 lines
19 KiB
Python
#!/usr/bin/env python3
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import argparse
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import logging
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import os
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import re
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import subprocess
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import tempfile
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import time
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import traceback
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import xml.etree.ElementTree as ET
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import gdstk
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import klayout.db as pya
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import klayout.rdb as rdb
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import yaml
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from klayout_tools import parse_lyp_layers
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from pin_check import pin_check
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from precheck_failure import PrecheckFailure
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from tech_data import (
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analog_pin_rects,
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boundary_layer,
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forbidden_layers,
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lyp_filename,
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tech_names,
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valid_layers,
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)
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PDK_ROOT = os.getenv("PDK_ROOT")
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PDK_NAME = os.getenv("PDK") or "sky130A"
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LYP_DIR = f"{PDK_ROOT}/{PDK_NAME}/libs.tech/klayout/tech"
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REPORTS_PATH = os.path.join(os.path.dirname(os.path.realpath(__file__)), "reports")
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if not PDK_ROOT:
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logging.error("PDK_ROOT environment variable not set")
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exit(1)
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def has_sky130_devices(gds: str):
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for cell_name in gdstk.read_rawcells(gds):
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if cell_name.startswith("sky130_fd_"):
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return True
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return False
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def load_layers(tech: str, only_valid: bool = True):
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lyp_file = f"{LYP_DIR}/{lyp_filename[tech]}"
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layers = parse_lyp_layers(lyp_file, only_valid)
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return layers
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def magic_drc(gds: str, toplevel: str):
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logging.info(f"Running magic DRC on {gds} (module={toplevel})")
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magic = subprocess.run(
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[
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"magic",
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"-noconsole",
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"-dnull",
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"-rcfile",
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f"{PDK_ROOT}/{PDK_NAME}/libs.tech/magic/{PDK_NAME}.magicrc",
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"magic_drc.tcl",
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gds,
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toplevel,
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PDK_ROOT,
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f"{REPORTS_PATH}/magic_drc.txt",
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f"{REPORTS_PATH}/magic_drc.mag",
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],
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)
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if magic.returncode != 0:
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if not has_sky130_devices(gds):
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logging.warning("No sky130 devices present - was the design flattened?")
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raise PrecheckFailure("Magic DRC failed")
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def klayout_custom_drc(
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check: str, script_path: str, script_vars: dict[str, str], report_vars: list[str]
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):
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report_file = f"{REPORTS_PATH}/drc_{check}.xml"
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klayout_args = ["klayout", "-b", "-r", script_path]
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for k, v in script_vars.items():
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klayout_args.extend(["-rd", f"{k}={v}"])
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for k in report_vars:
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klayout_args.extend(["-rd", f"{k}={report_file}"])
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klayout = subprocess.run(klayout_args)
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if klayout.returncode != 0:
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raise PrecheckFailure(f"Klayout {check} failed")
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report = rdb.ReportDatabase("DRC")
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report.load(report_file)
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if report.num_items() > 0:
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raise PrecheckFailure(
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f"Klayout {check} failed with {report.num_items()} DRC violations"
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)
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def klayout_drc(
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gds: str,
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check: str,
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script=f"{PDK_NAME}_mr.drc",
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script_dir="tech-files",
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extra_vars=[],
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):
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logging.info(f"Running klayout {check} on {gds}")
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if "/" not in script:
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script = f"{script_dir}/{script}"
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script_vars = {
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check: "true",
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"input": gds,
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"thr": "1", # single-threaded operation in sky130A_mr.drc to work around klayout bug
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}
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script_vars.update(extra_vars)
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klayout_custom_drc(check, script, script_vars, ["report", "report_file"])
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def klayout_zero_area(gds: str):
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return klayout_drc(gds, "zero_area", "zeroarea.rb.drc")
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def klayout_sg13g2(gds: str):
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return klayout_drc(
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gds,
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"sg13g2",
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f"{PDK_ROOT}/{PDK_NAME}/libs.tech/klayout/tech/drc/ihp-sg13g2.drc",
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)
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def klayout_gf180mcuD_antenna(gds: str):
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return klayout_drc(
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gds,
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"antenna",
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"antenna.drc",
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script_dir=f"{PDK_ROOT}/{PDK_NAME}/libs.tech/klayout/tech/drc/rule_decks",
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)
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def klayout_checks(gds: str, expected_name: str, tech: str):
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layout = pya.Layout()
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layout.read(gds)
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layers = load_layers(tech)
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logging.info("Running top macro name check...")
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top_cell = layout.top_cell()
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if top_cell.name != expected_name:
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raise PrecheckFailure(
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f"Top macro name mismatch: expected {expected_name}, got {top_cell.name}"
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)
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logging.info("Running forbidden layer check...")
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for layer in forbidden_layers[tech]:
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layer_info = layers[layer]
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logging.info(f"* Checking {layer_info.name}")
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layer_index = layout.find_layer(layer_info.layer, layer_info.data_type)
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if layer_index is not None:
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raise PrecheckFailure(f"Forbidden layer {layer} found in {gds}")
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logging.info("Running prBoundary check...")
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layer_name = boundary_layer[tech]
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layer_info = layers[layer_name]
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layer_index = layout.find_layer(layer_info.layer, layer_info.data_type)
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if layer_index is None:
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calma_index = f"{layer_info.layer}/{layer_info.data_type}"
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raise PrecheckFailure(f"{layer_name} ({calma_index}) layer not found in {gds}")
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def boundary_check(gds: str, tech: str):
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"""Ensure that there are no shapes outside the project area."""
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lib = gdstk.read_gds(gds)
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tops = lib.top_level()
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if len(tops) != 1:
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raise PrecheckFailure("GDS top level not unique")
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top = tops[0]
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boundary = top.copy("test_boundary")
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layers = load_layers(tech)
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layer_name = boundary_layer[tech]
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layer_info = layers[layer_name]
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boundary.filter([(layer_info.layer, layer_info.data_type)], False)
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if top.bounding_box() != boundary.bounding_box():
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raise PrecheckFailure("Shapes outside project area")
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def power_pin_check(verilog: str, lef: str, uses_vapwr: bool):
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"""Ensure that VPWR / VGND are present and have USE definitions,
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and that VAPWR is present if and only if 'uses_vapwr' is set."""
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verilog_s = open(verilog).read().replace("VPWR", "VDPWR")
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lef_s = open(lef).read().replace("VPWR", "VDPWR")
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# naive but good enough way to ignore comments
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verilog_s = re.sub("//.*", "", verilog_s)
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verilog_s = re.sub("/\\*.*?\\*/", "", verilog_s, flags=(re.DOTALL | re.MULTILINE))
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# this looks for a line beginning with "PIN", captures the name of the pin and the body up until its "END"
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PIN_PATTERN = re.compile(
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r"^\s*PIN (VPWR|VDPWR|VAPWR|VGND)\s*([\s\S]+?(?=^\s*END \1))",
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flags=re.MULTILINE,
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)
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for ft, s in (("Verilog", verilog_s), ("LEF", lef_s)):
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for pwr, ex in (("VGND", True), ("VDPWR", True), ("VAPWR", uses_vapwr)):
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if (pwr in s) and not ex:
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raise PrecheckFailure(f"{ft} contains {pwr}")
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if not (pwr in s) and ex:
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raise PrecheckFailure(f"{ft} doesn't contain {pwr}")
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for match in PIN_PATTERN.finditer(lef_s):
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pin, definition = match.groups()
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match pin:
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case "VPWR" | "VDPWR" | "VAPWR":
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if "USE POWER" not in definition:
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raise PrecheckFailure(
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f"{pin} does not have a corresponding 'USE POWER ;'"
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)
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case "VGND":
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if "USE GROUND" not in definition:
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raise PrecheckFailure(
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f"{pin} does not have a corresponding 'USE GROUND ;'"
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)
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case _:
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raise PrecheckFailure(f"unhandled {pin}")
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def layer_check(gds: str, tech: str):
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"""Check that there are no invalid layers in the GDS file."""
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layer_definition = load_layers(tech, only_valid=False)
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lib = gdstk.read_gds(gds)
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valid_layer_list = set(
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map(
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lambda layer_name: (
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(
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layer_definition[layer_name].layer,
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layer_definition[layer_name].data_type,
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)
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if type(layer_name) is str
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else layer_name
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),
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valid_layers[tech],
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)
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)
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gds_layers = lib.layers_and_datatypes().union(lib.layers_and_texttypes())
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excess = gds_layers - valid_layer_list
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if excess:
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raise PrecheckFailure(f"Invalid layers in GDS: {excess}")
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def cell_name_check(gds: str):
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"""Check that there are no cell names with '#' or '/' in them."""
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for cell_name in gdstk.read_rawcells(gds):
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if "#" in cell_name:
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raise PrecheckFailure(
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f"Cell name {cell_name} contains invalid character '#'"
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)
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if "/" in cell_name:
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raise PrecheckFailure(
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f"Cell_name {cell_name} contains invalid character '/'"
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)
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def urpm_nwell_check(gds: str, top_module: str):
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"""Run a DRC check for urpm to nwell spacing."""
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extra_vars = {"thr": os.cpu_count(), "top_cell": top_module}
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klayout_drc(
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gds=gds, check="nwell_urpm", script="nwell_urpm.drc", extra_vars=extra_vars
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)
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def analog_pin_check(
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gds: str,
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tech: str,
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is_analog: bool,
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uses_vapwr: bool,
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analog_pins: int,
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pinout: dict,
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):
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"""Check that every analog pin connects to a piece of metal
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if and only if the pin is used according to info.yaml."""
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if is_analog:
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lib = gdstk.read_gds(gds)
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top = lib.top_level()[0]
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filtered = {}
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for pin, (rect, pin_layer, via_layers) in enumerate(
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analog_pin_rects(tech, uses_vapwr)
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):
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for layer in [pin_layer] + via_layers:
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if layer not in filtered:
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i = len(filtered)
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lf = top.copy(f"test_lf_{i}")
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lf.flatten()
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lf.filter([layer], False)
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filtered[layer] = lf
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pin_rect = gdstk.rectangle(*rect)
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pin_ring = gdstk.boolean(
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gdstk.offset(pin_rect, 0.5), gdstk.offset(pin_rect, 0.1), "not"
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)
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pin_layer_polygons = filtered[pin_layer].polygons
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connected = bool(gdstk.boolean(pin_layer_polygons, pin_ring, "and"))
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for via_layer in via_layers:
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via_layer_polygons = filtered[via_layer].polygons
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connected = connected or bool(
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gdstk.boolean(via_layer_polygons, pin_rect, "and")
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)
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expected_pc = pin < analog_pins
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expected_pd = bool(pinout.get(f"ua[{pin}]", ""))
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if connected and not expected_pc:
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raise PrecheckFailure(
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f"Analog pin `ua[{pin}]` is connected to some metal but `analog_pins` is set to {analog_pins} in `info.yaml`. Either increase `analog_pins` to at least {pin+1}, or remove any metal or via adjacent to `ua[{pin}]`."
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)
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elif connected and not expected_pd:
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raise PrecheckFailure(
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f"Analog pin `ua[{pin}]` is connected to some metal but the description of `ua[{pin}]` in the pinout section of `info.yaml` is empty. Either add a description or remove any metal or via adjacent to `ua[{pin}]`."
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)
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elif not connected and expected_pc:
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raise PrecheckFailure(
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f"Analog pin `ua[{pin}]` is not connected to any adjacent metal but `analog_pins` is set to {analog_pins} in `info.yaml`. Either wire up `ua[{pin}]` to your design or decrease `analog_pins` to {pin}."
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)
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elif not connected and expected_pd:
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raise PrecheckFailure(
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f"Analog pin `ua[{pin}]` is not connected to any adjacent metal but the description of `ua[{pin}]` in the pinout section of `info.yaml` is non-empty. Either wire up `ua[{pin}]` to your design or remove the description for the disconnected pin."
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)
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def verilog_syntax_check(verilog: str):
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"""Load the Verilog file into Yosys to verify it can be read successfully."""
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logging.info(f"Running Verilog syntax check on {verilog}")
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verilog_dir = os.path.dirname(verilog)
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yowasp_env = os.environ.copy()
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yowasp_env["YOWASP_MOUNT"] = f"{verilog_dir}={verilog_dir}"
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yosys = subprocess.run(
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[
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"yowasp-yosys",
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"-p",
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f'read_verilog -sv "{verilog}"',
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],
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env=yowasp_env,
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)
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if yosys.returncode != 0:
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raise PrecheckFailure("Verilog syntax check failed")
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def main():
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default_tech = PDK_NAME
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if default_tech not in tech_names:
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default_tech = tech_names[0]
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parser = argparse.ArgumentParser()
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parser.add_argument("--gds", required=True)
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parser.add_argument(
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"--tech", required=False, default=default_tech, choices=tech_names
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)
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args = parser.parse_args()
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logging.basicConfig(level=logging.INFO, format="%(levelname)s: %(message)s")
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logging.info(f"PDK_ROOT: {PDK_ROOT}")
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logging.info(f"Tech: {args.tech}")
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if args.gds.endswith(".gds"):
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gds_stem = args.gds.removesuffix(".gds")
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gds_temp = None
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gds_file = args.gds
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elif args.gds.endswith(".oas"):
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gds_stem = args.gds.removesuffix(".oas")
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gds_temp = tempfile.NamedTemporaryFile(suffix=".gds", delete=False)
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gds_file = gds_temp.name
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logging.info(f"Converting {args.gds} to {gds_file}")
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layout = pya.Layout()
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layout.read(args.gds)
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layout.write(gds_file)
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else:
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raise PrecheckFailure("Layout file extension is neither .gds nor .oas")
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tech = args.tech
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if tech not in tech_names:
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raise PrecheckFailure(f"Invalid tech: {tech}")
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yaml_dir = os.path.dirname(args.gds)
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while not os.path.exists(f"{yaml_dir}/info.yaml"):
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yaml_dir = os.path.dirname(yaml_dir)
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if yaml_dir in ("/", ""):
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raise PrecheckFailure("info.yaml not found")
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yaml_file = f"{yaml_dir}/info.yaml"
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yaml_data = yaml.safe_load(open(yaml_file))
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wokwi_id = yaml_data["project"].get("wokwi_id", 0)
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top_module = yaml_data["project"].get("top_module", f"tt_um_wokwi_{wokwi_id}")
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assert top_module == os.path.basename(gds_stem)
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project_cfg = yaml_data.get("project", {})
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tiles = project_cfg.get("tiles", "1x1")
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analog_pins = project_cfg.get("analog_pins", 0)
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is_analog = analog_pins > 0
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# "uses_3v3" is the legacy name for "uses_vapwr"; still accepted for compat.
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uses_vapwr = bool(project_cfg.get("uses_vapwr", project_cfg.get("uses_3v3", False)))
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pinout = yaml_data.get("pinout", {})
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if uses_vapwr and not is_analog:
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raise PrecheckFailure("Projects with VAPWR power need at least one analog pin")
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def_root = f"../tech/{tech}/def"
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if is_analog:
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analog_def = f"{def_root}/analog/tt_analog_{tiles}"
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if uses_vapwr:
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# gf180's second supply rail is "pgvaa" (its core is already 3v3, so
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# "_3v3" is a misnomer); fall back to "_3v3" for techs that use it.
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template_def = f"{analog_def}_pgvaa.def"
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if not os.path.exists(template_def):
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template_def = f"{analog_def}_3v3.def"
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else:
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template_def = f"{analog_def}.def"
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elif tech == "ihp-sg13g2" or tech == "gf180mcuD":
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template_def = f"{def_root}/tt_block_{tiles}_pgvdd.def"
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else:
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template_def = f"{def_root}/tt_block_{tiles}_pg.def"
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logging.info(f"using def template {template_def}")
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gds_dir = os.path.dirname(gds_stem)
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lef_file = gds_stem + ".lef"
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lef_file_alt = os.path.join(
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gds_dir, "..", "lef", os.path.basename(gds_stem) + ".lef"
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)
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if not os.path.exists(lef_file) and os.path.exists(lef_file_alt):
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lef_file = lef_file_alt
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verilog_file = gds_stem + ".v"
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checks = [
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{
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"name": "Magic DRC",
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"check": lambda: magic_drc(gds_file, top_module),
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"techs": ["sky130A"],
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},
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{
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"name": "KLayout FEOL",
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"check": lambda: klayout_drc(gds_file, "feol"),
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"techs": ["sky130A"],
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},
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{
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"name": "KLayout BEOL",
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"check": lambda: klayout_drc(gds_file, "beol"),
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"techs": ["sky130A"],
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},
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{
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"name": "KLayout offgrid",
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"check": lambda: klayout_drc(gds_file, "offgrid"),
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"techs": ["sky130A"],
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},
|
|
{
|
|
"name": "KLayout pin label overlapping drawing",
|
|
"check": lambda: klayout_drc(
|
|
gds_file,
|
|
"pin_label_purposes_overlapping_drawing",
|
|
"pin_label_purposes_overlapping_drawing.rb.drc",
|
|
),
|
|
},
|
|
{
|
|
"name": "KLayout SG13G2 DRC",
|
|
"check": lambda: klayout_sg13g2(gds_file),
|
|
"techs": ["ihp-sg13g2"],
|
|
},
|
|
{"name": "KLayout zero area", "check": lambda: klayout_zero_area(gds_file)},
|
|
{
|
|
"name": "KLayout Checks",
|
|
"check": lambda: klayout_checks(gds_file, top_module, tech),
|
|
},
|
|
{
|
|
"name": "Pin check",
|
|
"check": lambda: pin_check(
|
|
gds_file, lef_file, template_def, top_module, uses_vapwr, tech
|
|
),
|
|
},
|
|
{"name": "Boundary check", "check": lambda: boundary_check(gds_file, tech)},
|
|
{
|
|
"name": "Power pin check",
|
|
"check": lambda: power_pin_check(verilog_file, lef_file, uses_vapwr),
|
|
"techs": ["sky130A", "gf180mcuD"],
|
|
},
|
|
{"name": "Layer check", "check": lambda: layer_check(gds_file, tech)},
|
|
{"name": "Cell name check", "check": lambda: cell_name_check(gds_file)},
|
|
{
|
|
"name": "urpm/nwell check",
|
|
"check": lambda: urpm_nwell_check(gds_file, top_module),
|
|
"techs": ["sky130A"],
|
|
},
|
|
{
|
|
"name": "Antenna check",
|
|
"check": lambda: klayout_gf180mcuD_antenna(gds_file),
|
|
"techs": ["gf180mcuD"],
|
|
},
|
|
{
|
|
"name": "Analog pin check",
|
|
"check": lambda: analog_pin_check(
|
|
gds_file, tech, is_analog, uses_vapwr, analog_pins, pinout
|
|
),
|
|
"techs": ["sky130A", "ihp-sg13g2", "gf180mcuD"],
|
|
},
|
|
{
|
|
"name": "Verilog syntax check",
|
|
"check": lambda: verilog_syntax_check(verilog_file),
|
|
},
|
|
]
|
|
|
|
testsuite = ET.Element("testsuite", name="Tiny Tapeout Prechecks")
|
|
error_count = 0
|
|
markdown_table = "# Tiny Tapeout Precheck Results\n\n"
|
|
markdown_table += "| Check | Result |\n|-----------|--------|\n"
|
|
for check in checks:
|
|
name = check["name"]
|
|
if "techs" in check and tech not in check["techs"]:
|
|
continue
|
|
start_time = time.time()
|
|
test_case = ET.SubElement(testsuite, "testcase", name=name)
|
|
try:
|
|
check["check"]()
|
|
elapsed_time = time.time() - start_time
|
|
markdown_table += f"| {name} | ✅ |\n"
|
|
test_case.set("time", str(round(elapsed_time, 2)))
|
|
except Exception as e:
|
|
error_count += 1
|
|
elapsed_time = time.time() - start_time
|
|
markdown_table += f"| {name} | ❌ Fail: {str(e)} |\n"
|
|
test_case.set("time", str(round(elapsed_time, 2)))
|
|
error = ET.SubElement(test_case, "error", message=str(e))
|
|
error.text = traceback.format_exc()
|
|
markdown_table += "\n"
|
|
markdown_table += "In case of failure, please reach out on [discord](https://tinytapeout.com/discord) for assistance."
|
|
|
|
testsuites = ET.Element("testsuites")
|
|
testsuites.append(testsuite)
|
|
xunit_report = ET.ElementTree(testsuites)
|
|
ET.indent(xunit_report, space=" ", level=0)
|
|
xunit_report.write(f"{REPORTS_PATH}/results.xml", encoding="unicode")
|
|
|
|
with open(f"{REPORTS_PATH}/results.md", "w") as f:
|
|
f.write(markdown_table)
|
|
|
|
if gds_temp is not None:
|
|
gds_temp.close()
|
|
os.unlink(gds_temp.name)
|
|
|
|
if error_count > 0:
|
|
logging.error(f"Precheck failed for {args.gds}! 😭")
|
|
logging.error(f"See {REPORTS_PATH} for more details")
|
|
logging.error(f"Markdown report:\n{markdown_table}")
|
|
exit(1)
|
|
else:
|
|
logging.info(f"Precheck passed for {args.gds}! 🎉")
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|