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37 lines
866 B
Verilog
37 lines
866 B
Verilog
/*
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* tt_um_chip_rom.v
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*
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* ROM module for Tiny Tapeout chips. The layout of the ROM is documented at
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* https://github.com/TinyTapeout/tt-chip-rom/blob/main/docs/info.md.
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*
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* Author: Uri Shaked
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*/
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`default_nettype none
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`ifndef ROM_VMEM_PATH
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`define ROM_VMEM_PATH "rom.vmem"
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`endif
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module tt_um_chip_rom (
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input wire [7:0] ui_in, // Dedicated inputs
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output wire [7:0] uo_out, // Dedicated outputs
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input wire [7:0] uio_in, // IOs: Input path
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output wire [7:0] uio_out,// IOs: Output path
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output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output)
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input wire ena,
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input wire clk,
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input wire rst_n
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);
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reg [7:0] rom_data [0:255];
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initial begin
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$readmemh(`ROM_VMEM_PATH, rom_data);
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end
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assign uo_out = rom_data[ui_in];
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assign uio_out = 8'h00;
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assign uio_oe = 8'h00;
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endmodule // tt_um_chip_rom
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